參數(shù)資料
型號(hào): M37545G8-XXXGP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP32
封裝: 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁(yè)數(shù): 39/63頁(yè)
文件大?。?/td> 774K
代理商: M37545G8-XXXGP
Rev.1.07
Mar 19, 2009
Page 44 of 60
REJ03B0140-0107
7545 Group
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after reset are
undefined except for the interrupt disable flag I which is “1”.
After reset, initialize flags which affect program execution. In
particular, it is essential to initialize the T flag and the D flag
because of their effect on calculations. Initialize these flags at
beginning of the program.
Interrupts
The contents of the interrupt request bit do not change even if the
BBC or BBS instruction is executed immediately after they are
changed by program because this instruction is executed for the
previous contents. For executing the instruction for the changed
contents, execute one instruction before executing the BBC or
BBS instruction.
Decimal Calculations
For calculations in decimal notation, set the decimal mode flag
D to “1”, then execute the ADC instruction or SBC instruction.
In this case, execute SEC instruction, CLC instruction or CLD
instruction after executing one instruction before the ADC
instruction or SBC instruction.
In the decimal mode, the values of the N (negative), V
(overflow) and Z (zero) flags are invalid.
Ports
The values of the port direction registers cannot be read.
That is, it is impossible to use the LDA instruction, memory
operation instruction when the T flag is “1”, addressing mode
using direction register values as qualifiers, and bit test
instructions such as BBC and BBS.
It is also impossible to use bit operation instructions such as CLB
and SEB and read/modify/write instructions of direction registers
for calculations such as ROR.
For setting direction registers, use the LDM instruction, STA
instruction, etc.
Instruction Execution Timing
The instruction execution time can be obtained by multiplying
the frequency of the internal clock
φ by the number of cycles
mentioned in the machine-language instruction table.
The frequency of the internal clock
φ is 4 times the XIN cycle.
CPU Mode Register
The processor mode bits can be rewritten only once after
releasing reset. However, after rewriting it is disable to write any
value to the bit. (Emulator MCU is excluded.)
NOTES ON HARDWARE
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor
suitable for high frequencies as bypass capacitor between power
source pin (VCC pin) and GND pin (VSS pin). Besides, connect
the capacitor to as close as possible. For bypass capacitor which
should not be located too far from the pins to be connected, a
ceramic capacitor of 0.01
F to 0.1 F is recommended.
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