參數(shù)資料
型號： M37542M4-XXXHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQCC36
封裝： 6 X 6 MM, 0.50 MM PITCH, PLASTIC, WQFN-36
文件頁數(shù)： 96/122頁
文件大?。?/td> 1311K
代理商： M37542M4-XXXHP
7542 Group
Rev.3.03
Jul 11, 2008
Page 75 of 117
REJ03B0006-0303
Fig. 98 Structure of flash memory control register 0
b7
b0
Flash memory control register 0
(FMCR0: address : 0FE016: initial value: 0116)
RY/BY
status flag
0 : Busy (being written or erased)
1 : Ready
CPU rewrite mode select bit (Note 1)
0 :
CPU rewrite mode invalid
1 :
CPU rewrite mode valid
8KB user block E/W mode enable bit
(Note 1, 2)
0 : E/W disabled
1 : E/W enabled
Flash memory reset bit
(Note 3)
0 : Normal operation
1 : reset
Not used (do not write “1” to this bit.)
User ROM area select bit
(Note 4)
0 : Boot ROM area is accessed
1 : User ROM area is accessed
Program status flag
0: Pass
1: Error
Erase status flag
0: Pass
1: Error
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
“1” to it in succession. For this bit to be set to “0”, write “0” only to
this bit.
2: This bit can be written only when CPU rewrite mode select bit is “1”.
3: Effective only when the CPU rewrite mode select bit = “1”. Fix this
bit to “0” when the CPU rewrite mode select bit is “0”.
4: Write to this bit in program on RAM
[Flash memory control registers (FMCR0 to FMCR2)]
0FE016 to 0FE216
Figure 98 shows the flash memory control register 0.
Bit 0 of the flash memory control register 0 is the RY/BY status
flag used exclusively to read the operating status of the flash
memory. During programming and erase operations, it is “0”
(busy). Otherwise, it is “1” (ready).
Bit 1 of the flash memory control register 0 is the CPU rewrite
mode select bit. When this bit is set to “1”, the MCU enters CPU
rewrite mode. And then, software commands can be accepted. In
CPU rewrite mode, the CPU becomes unable to access the inter-
nal flash memory directly. Therefore, use the control program in
the internal RAM for write to bit 1. To set this bit 1 to “1”, it is nec-
essary to write “0” and then write “1” in succession to bit 1. The bit
can be set to “0” by only writing “0”.
Bit 2 of the flash memory control register 0 is the 8KB user block
E/W mode enable bit. By setting this bit in combination with bit 4
(all user block E/W enable bit) of flash memory control register 2
(address 0FE016), Erase/Write to user block in CPU rewrite mode
is disabled.
Bit 3 of the flash memory control register 0 is the flash memory re-
set bit used to reset the control circuit of internal flash memory.
This bit is used when exiting CPU rewrite mode and when flash
memory access has failed. When the CPU rewrite mode select bit
is “1”, setting “1” for this bit resets the control circuit. To release
the reset, it is necessary to set this bit to “0”.
Bit 5 of the flash memory control register 0 is the User ROM area
select bit and is valid only in the boot mode. Setting this bit to “1”
in the boot mode switches an accessible area from the boot ROM
area to the user ROM area. To use the CPU rewrite mode in the
boot mode, set this bit to “1”. Note that when the microcomputer is
booted up in the user ROM area, only the user ROM area is ac-
cessible and bit 5 is invalid; on the other hand, when the
microcomputer is in the boot mode, bit 5 is valid independent of
the CPU rewrite mode. To rewrite bit 5, execute the user-original
reprogramming control software transferred to the internal RAM in
advance.
Bit 6 of the flash memory control register 0 is the program status
flag. This bit is set to “1” when writing to flash memory is failed.
When program error occurs, the block cannot be used.
Bit 7 of the flash memory control register 0 is the erase status flag.
This bit is set to “1” when erasing flash memory is failed. When
erase error occurs, the block cannot be used.
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