參數(shù)資料
型號(hào)： M37542F8SP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32
封裝： 8.9 X 28 MM, 1.78 MM PITCH, PLASTIC, SDIP-32
文件頁數(shù)： 46/124頁
文件大?。?/td> 1238K
代理商： M37542F8SP
7542 Group
Rev.3.03
Jul 11, 2008
Page 26 of 117
REJ03B0006-0303
Fig. 23 Interrupt control
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Interrupt acceptance
Interrupt Disable Flag
The interrupt disable flag is assigned to bit 2 of the processor sta-
tus register. This flag controls the acceptance of all interrupt
requests except for the BRK instruction. When this flag is set to
“1”, the acceptance of interrupt requests is disabled. When it is set
to “0”, the acceptance of interrupt requests is enabled. This flag is
set to “1” with the SEI instruction and set to “0” with the CLI in-
struction.
When an interrupt request is accepted, the contents of the proces-
sor status register are pushed onto the stack while the interrupt
disable flag remains set to “0”. Subsequently, this flag is automati-
cally set to “1” and multiple interrupts are disabled.
To use multiple interrupts, set this flag to “0” with the CLI instruc-
tion within the interrupt processing routine.
The contents of the processor status register are popped off the
stack with the RTI instruction.
Interrupt Request Bits
Once an interrupt request is generated, the corresponding inter-
rupt request bit is set to “1” and remains “1” until the request is
accepted. When the request is accepted, this bit is automatically
set to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to
“1”, by software.
Interrupt Enable Bits
The interrupt enable bits control the acceptance of the corre-
sponding interrupt requests. When an interrupt enable bit is set to
“0”, the acceptance of the corresponding interrupt request is dis-
abled. If an interrupt request occurs in this condition, the
corresponding interrupt request bit is set to “1”, but the interrupt
request is not accepted. When an interrupt enable bit is set to “1”,
the acceptance of the corresponding interrupt request is enabled.
Each interrupt enable bit can be set to “0” or “1” by software.
The interrupt enable bit for an unused interrupt should be set to
“0”.
Interrupt Enable Setting
The following interrupt sources can be set to valid or invalid by the
interrupt source set register (000A16).
Key-on wakeup
UART1 bus collision detection interrupt
A/D conversion
Timer 1 interrupt
External Interrupt Pin Selection
For the external interrupt INT1, the external input pin P33 or P36
can be selected by the INT1 input port selection bit in the interrupt
edge selection register (bit 2 of address 003A16).
However, since there is no P36/INT1 pin in the 32-pin version
PWQN0036KA-A package, select P33/INT1 pin. By the key-on
wakeup selection bit, enable/disable of a key-on wakeup of P00,
P04, and P06 pins can be selected, respectively.
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參數(shù)描述
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