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參數資料
| 型號： | M37542F8GP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32 |
| 封裝： | 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32 |
| 文件頁數： | 18/124頁 |
| 文件大小： | 1238K |
| 代理商： | M37542F8GP |
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7542 Group
Rev.3.03
Jul 11, 2008
Page 112 of 117
REJ03B0006-0303
Notes on Output Compare
1. When the selected source timer of each compare channel is
stopped, written data to compare register is loaded to the com-
pare latch simultaneously.
2. Do not write the same data to both of compare latch x0 (x=0, 1,
2, 3) and x1.
3. When setting value of the compare register is larger than timer
setting value, compare match signal is not generated. Accord-
ingly, the output waveform is fixed to “L” or “H” level.
However, when setting value of another compare register is
smaller than timer setting value, this compare match signal is
generated. Accordingly, if the corresponding compare latch y
(y=00, 01, 10, 11, 20, 21, 30, 31) interrupt source bit is set to “1”
(valid), compare match interrupt request occurs.
4. When the compare x trigger enable bit is cleared to “0” (dis-
abled), the match trigger to the waveform output circuit is
disabled. Accordingly, the output waveform can be fixed to “L”
or “H” level.
However, in this case, the compare match signal is generated.
Accordingly, if the corresponding compare latch y (y=00, 01, 10,
11, 20, 21, 30, 31) interrupt source bit is set to “1”
(valid),compare match interrupt request occurs.
Notes on Input Capture
1. If the capture trigger is input while the capture register (low-or-
der and high-order) is in read, captured value is changed
between high-order reading and low-order reading. Accordingly,
some countermeasure by software is recommended, for ex-
ample comparing the values that twice of read.
2. Timer A cannot be used for the capture source timer in the fol-
lowing state;
XIN oscillation selected by clock division ratio selection bits
(bits 7 and 6 of CPU mode register (address 3B16))
Timer A count source: On-chip oscillator output.
Timer B cannot be used for the capture source timer in the fol-
lowing state;
XIN oscillation selected by clock division ratio selection bits
Timer B count source: Timer A underflow
Timer A count source: On-chip oscillator output.
3. As shown below, when the capture input is performed to both
capture latch 00 and 01 at the same time, the value of capture
0 status bit (bit 4 of capture/compare status register (address
2216)) is undefined (same as capture 1).
When “1” is written to capture latch 00 software trigger bit (bit 0
of capture software trigger register (address 1316)) and capture
latch 01 software trigger bit (bit 1 of capture software trigger reg-
ister) at the same time
When external trigger of capture latch 00 and software trigger of
capture latch 01 occur at the same time
When external trigger of capture latch 01 and software trigger of
capture latch 00 occur at the same time
4. When the capture interrupt is used as the interrupt for return
from stop mode, set the capture 0 noise filter clock selection
bits (bits 5 and 4 of capture mode register (address 2016)) to
“00 (Filter stop)” (same as capture 1).
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| M37542M4-XXXHP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQCC36 |
| M37542M2-XXXFP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO36 |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| M37542F8GP#U0 | 功能描述:MCU 3/5V 32K+4K PB-FREE 32-LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 標準包裝:250 系列:80C 核心處理器:8051 芯體尺寸:8-位 速度:16MHz 連通性:EBI/EMI，I²C，UART/USART 外圍設備:POR，PWM，WDT 輸入/輸出數:40 程序存儲器容量:- 程序存儲器類型:ROMless EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數據轉換器:A/D 8x10b 振蕩器型:內部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-LCC（J 形引線） 包裝:帶卷 (TR) |
| M37542F8GPSP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP MICROCOMPUTER |
| M37542F8HP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37542F8SP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37542F8SP#U0 | 制造商:Renesas Electronics Corporation 功能描述:MCU 4.0/5.5V 32K PB-FREE 32-SDIP - Trays |
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