參數(shù)資料
型號： M37542F4SP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32
封裝： 8.9 X 28 MM, 1.78 MM PITCH, PLASTIC, SDIP-32
文件頁數(shù)： 66/122頁
文件大?。?/td> 1311K
代理商： M37542F4SP
7542 Group
Rev.3.03
Jul 11, 2008
Page 48 of 117
REJ03B0006-0303
Fig. 57 Block diagram of UART serial I/O1
(2) Asynchronous Serial I/O1 (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit of the serial I/O1 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Fig. 58 Operation of UART serial I/O1 function
XIN
1/4
OE
PE FE
1/16
Data bus
Receive buffer register 1
Address 001816
Receive shift register 1
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Baud rate generator 1
Frequency division ratio 1/(n+1)
Address 001C16
ST/SP/PA generator
Transmit buffer register 1
Data bus
Transmit shift register 1
Address 001816
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Address 001916
ST detector
SP detector
UART1 control register
Address 001B16
Character length selection bit
Address 001A16
BRG count source selection bit
Transmit interrupt source selection bit
Serial I/O1 synchronous clock selection bit
Clock control circuit
Character length selection bit
7 bits
8 bits
Serial I/O1 control register
P12/SCLK1
Serial I/O1 status register
P10/RXD1/CAP0
P11/TXD1
TSC=0
TBE=1
RBF=0
TBE=0
RBF=1
ST
D0
D1
SP
D0
D1
ST
SP
TBE=1
TSC=1
ST
D0
D1
SP
D0
D1
ST
SP
Transmit or receive clock
Transmit buffer 1
write signal
Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Notes
Serial output TXD1
Serial input RXD1
Receive buffer 1
read signal
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