參數(shù)資料
型號: M37542F4SP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32
封裝: 8.9 X 28 MM, 1.78 MM PITCH, PLASTIC, SDIP-32
文件頁數(shù): 45/122頁
文件大小: 1311K
代理商: M37542F4SP
7542 Group
Rev.3.03
Jul 11, 2008
Page 29 of 117
REJ03B0006-0303
Fig. 27 Timing of interrupt request generation, interrupt request bit, and interrupt acceptance
Instruction cycle
Push onto stack
Vector fetch
Instruction cycle
Internal clock φ
SYNC
T1
IR1 T2
IR2 T3
T1 T2 T3 : Interrupt acceptance timing points
IR1 IR2 : Timings points at which the interrupt request bit is set to “1”.
Note : Period 2 indicates the last φ cycle during one instruction cycle.
(1) The interrupt request bit for an interrupt request generated during period 1 is set to “1” at timing point IR1.
(2) The interrupt request bit for an interrupt request generated during period 2 is set to “1” at timing point IR1 or IR2.
The timing point at which the bit is set to “1” varies depending on conditions. When two or more interrupt
requests are generated during the period 2, each request bit may be set to “1” at timing point IR1 or IR2
separately.
Fig. 26 Interrupt sequence
φ
SYNC
RD
WR
Address bus
Data bus
PC
Not used
S,SPS
S-1,SPS S-2,SPS
BL
BH
AL,AH
PCH
PCL
PS
AL
AH
SYNC : CPU operation code fetch cycle
(This is an internal signal that cannot be observed from the external unit.)
BL, BH : Vector address of each interrupt
AL, AH : Jump destination address of each interrupt
SPS
: “0016” or “0116
([SPS] is a page selected by the stack page selection bit of CPU mode register.)
Push onto stack
Vector fetch
Execute interrupt
routine
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