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參數(shù)資料
| 型號： | M37542F4FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO36 |
| 封裝： | 8.4 X 15 MM, 0.80 MM PITCH, PLASTIC, SSOP-36 |
| 文件頁數(shù)： | 19/124頁 |
| 文件大小： | 1238K |
| 代理商： | M37542F4FP |
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7542 Group
Rev.3.03
Jul 11, 2008
Page 113 of 117
REJ03B0006-0303
3. Notes common to clock synchronous serial I/O and UART
(1) Set the serial I/Oi (i=1, 2) control register again after the trans-
mission and the reception circuits are reset by clearing both
the transmit enable bit and the receive enable bit to “0.”
Fig. 6 Sequence of setting serial I/Oi control register again
Clear both the transmit enable bit (TE)
and the receive enable bit (RE) to “0”
Set the bits 0 to 3 and bit 6 of the
serial I/Oi control register
Set both the transmit enable bit (TE)
and the receive enable bit (RE), or
one of them to “1”
Notes on Serial I/Oi (i=1, 2)
1. Clock synchronous serial I/O
(1) When the transmit operation is stopped, clear the serial I/Oi
enable bit and the transmit enable bit to “0” (serial I/Oi and
transmit disabled).
<Reason>
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/Oi enable bit is cleared to “0”
(serial I/Oi disabled), the internal transmission is running (in this
case, since pins TxDi, RxDi, SCLKi, and SRDYi function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/Oi enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxDi pin and an operation failure occurs.
(2) When the receive operation is stopped, clear the receive en-
able bit to “0” (receive disabled), or clear the serial I/Oi enable
bit to “0” (serial I/Oi disabled).
(3) When the transmit/receive operation is stopped, clear both the
transmit enable bit and receive enable bit to “0” (transmit and
receive disabled) simultaneously. (any one of data transmis-
sion and reception cannot be stopped.)
<Reason>
In the clock synchronous serial I/O mode, the same clock is used
for transmission and reception.
If any one of transmission and reception is disabled, a bit error oc-
curs because transmission and reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also oper-
ates for data reception. Accordingly, the transmission circuit does
not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit cannot be initialized even
if the serial I/Oi enable bit is cleared to “0” (serial I/Oi disabled)
(same as (1)).
(4) When signals are output from the SRDYi pin on the reception
side by using an external clock, set all of the receive enable
bit, the SRDYi output enable bit, and the transmit enable bit to
“1”.
(5) When the SRDYi signal input is used, set the using pin to the in-
put mode before data is written to the transmit/receive buffer
register.
2. UART
When the transmit operation is stopped, clear the transmit enable
bit to “0” (transmit disabled).
<Reason>
Same as (1) shown on the above “1. Clock synchronous serial I/O“.
When the receive operation is stopped, clear the receive enable
bit to “0” (receive disabled).
When the transmit/receive operation is stopped, clear the transmit
enable bit to “0” (transmit disabled) and receive enable bit to “0”
(receive disabled).
(2) The transmit shift completion flag changes from “1” to “0” with
a delay of 0.5 to 1.5 shift clocks. When data transmission is
controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(3) When data transmission is executed at the state that an exter-
nal clock input is selected as the synchronous clock, set “1” to
the transmit enable bit while the SCLKi is “H” state. Also, write
to the transmit buffer register while the SCLKi is “H” state.
(4) When the transmit interrupt is used, set as the following se-
quence.
Serial I/Oi transmit interrupt enable bit is set to “0” (disabled).
Serial I/Oi transmit enable bit is set to “1”.
Serial I/Oi transmit interrupt request bit is set to “0” after 1 or
more instructions have been executed.
Serial I/Oi transmit interrupt enable bit is set to “1” (enabled).
<Reason>
When the transmit enable bit is set to “1”, the transmit buffer
empty flag and transmit shift completion flag are set to “1”.
Accordingly, even if the timing when any of the above flags is set
to “1” is selected for the transmit interrupt source, interrupt request
occurs and the transmit interrupt request bit is set.
(5) Write to the baud rate generator (BRGi) while the transmit/re-
ceive operation is stopped.
Can be set
with the LDM
instruction at
the same time
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