參數(shù)資料
型號: M37534E4GP
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 46/55頁
文件大?。?/td> 610K
代理商: M37534E4GP
7534 Group
Rev.2.00 Jun 21, 2004 page 46 of 54
REJ03B0099-0200Z
Differences among 32-pin, 36-pin and 42-pin
The 7534 Group has three package types, and each of the number
of I/O ports are different. Accordingly, when the pins which have the
function except a port function are eliminated, be careful that the
functions are also eliminated.
Table 15 Differences among 32-pin, 36-pin and 42-pin
I/O port
Port P1
Port P2
P2
0
–P2
7
(8-bit structure)
(A/D converter 8-channel)
P3
0
–P3
7
(8-bit structure)
(INT
0
, INT
1
available)
P4
0
, P4
1
(2-bit structure)
Port P3
Port P4
42-pin SDIP
P1
0
–P1
6
(7-bit structure)
36-pin SSOP
P1
0
–P1
4
(5-bit structure)
P2
0
–P2
7
(8-bit structure)
(A/D converter 8-channel)
P3
0
–P3
5
, P3
7
(7-bit structure)
(INT
0
available)
No port
32-pin LQFP
P1
0
–P1
4
(5-bit structure)
P2
0
–P2
5
(6-bit structure)
(A/D converter 6-channel)
P3
0
–P3
4
(5-bit structure)
(INT function not available)
No port
Description of improved USB function for 7534
Group
Table 14 Description of improved USB function for 7534 Group
Parameter
Response at Control transfer
No.
1
2
3
4
5
D+/D- transceiver circuit
Power dissipation at Suspend
STALL in Status stage
6-bit decode of SYNC field
7532/7536 Group
Not deal with the host which performs the Control
transfer in parallel to plural device.
USB function can be used only at the condition of
C
L
= 150 pF to 350 pF.
Rating is Max. 300
μ
A not including the output cur-
rent of USBV
REFOUT
.
ACK is returned once to OUT (DATA0) to be valid
in Status stage.
SYNC is detected only when 8-bit full code (80
16
)
is complete.
7534 Group
Connectable to the host which performs the Con-
trol transfer in parallel to plural device.
Deal with the the following USB Spefification Rev.
1.1.
C
L
= 200 pF to 450 pF,
Trise and Tfall: 75 ns to 300 ns,
Tr/Tf: 80 % to 125 %,
Cross over Voltage: 1.3 V to 2.0 V.
Rating is Max. 300
μ
A including the output current
of USBV
REFOUT
, by low-power dissipation of D+/
D- input circuit and 3.3 V-regulator.
STALL is set automaticcally by hardware when
OUT (DATA0) is received in Status stage.
SYNC is detected only the low-order 6 bits even if
the high-order 2 bits are corrupted.
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