參數(shù)資料
型號(hào)： M37516M6-A05
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 33/54頁(yè)
文件大?。?/td> 358K
代理商： M37516M6-A05
33/54
M37516M6-XXXHP
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
PA
GE
Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is
shown below.
(1) Set a slave address in the high-order 7 bits of the I
2
C address
register (address 002C
16
) and “0” into the RWB bit.
(2) Set the ACK return mode and SCL = 100 kHz by setting “85
16
”
in the I
2
C clock control register (address 002F
16
).
(3) Set “00
16
” in the I
2
C status register (address 002D
16
) so that
transmission/reception mode can become initializing condition.
(4) Set a communication enable status by setting “08
16
” in the I
2
C
control register (address 002E
16
).
(5) Confirm the bus free condition by the BB flag of the I
2
C status
register (address 002D
16
).
(6) Set the address data of the destination of transmission in the
high-order 7 bits of the I
2
C data shift register (address 002B
16
)
and set “0” in the least significant bit.
(7) Set “F0
16
” in the I
2
C status register (address 002D
16
) to gener-
ate a START condition. At this time, an SCL for 1 byte and an
ACK clock automatically occur.
(8) Set transmit data in the I
2
002B
16
). At this time, an SCL and an ACK clock automatically
occur.
(9) When transmitting control data of more than 1 byte, repeat
step (8).
(10) Set “D0
16
” in the I
2
C status register (address 002D
16
) to gen-
erate a STOP condition if ACK is not returned from slave
reception side or transmission ends.
Example of Slave Reception
An example of slave reception in the high-speed clock mode, at
the SCL frequency of 400 kHz, in the ACK non-return mode and
using the addressing format is shown below.
(1) Set a slave address in the high-order 7 bits of the I
2
C address
register (address 002C
16
) and “0” in the RWB bit.
(2) Set the no ACK clock mode and SCL = 400 kHz by setting
“25
16
” in the I
2
C clock control register (address 002F
16
).
(3) Set “00
16
” in the I
2
C status register (address 002D
16
) so that
transmission/reception mode can become initializing condition.
(4) Set a communication enable status by setting “08
16
” in the I
2
C
control register (address 002E
16
).
(5) When a START condition is received, an address comparison
is performed.
(6)
When all transmitted addresses are “0” (general call):
AD0 of the I
2
C status register (address 002D
16
) is set to “1”
and an interrupt request signal occurs.
When the transmitted addresses agree with the address set
in (1):
ASS of the I
2
C status register (address 002D
16
) is set to “1”
and an interrupt request signal occurs.
In the cases other than the above AD0 and AAS of the I
2
C sta-
tus register (address 002D
16
) are set to “0” and no interrupt
request signal occurs.
(7) Set dummy data in the I
2
C data shift register (address
002B
16
).
(8) When receiving control data of more than 1 byte, repeat step
(7).
(9) When a STOP condition is detected, the communication ends.
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