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參數資料
| 型號： | M37516M6-A05 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數： | 32/54頁 |
| 文件大小： | 358K |
| 代理商： | M37516M6-A05 |
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M37516M6-XXXHP
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
PA
GE
START/STOP
condition
control register
XXX11010
XXX11000
XXX00100
XXX01100
XXX01010
XXX00100
Oscillation
frequency
f(X
IN
) (MHz)
Fig. 35 Address data communication format
Fig. 34 Structure of I
2
C START/STOP condition control register
Note:
Do not set “00000
2
” or an odd number to the START/STOP condition set bit (SSC4 to SSC0).
Table 9 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency
Main clock
divide ratio
System
clock
φ
(MHz)
SCL release time
(
μ
s)
Setup time
(
μ
s)
Hold time
(
μ
s)
8
8
4
2
2
8
2
2
3.375
μ
s (13.5 cycles)
3.125
μ
s (12.5 cycles)
2.5
μ
s (2.5 cycles)
3.25
μ
s (6.5 cycles)
2.75
μ
s (5.5 cycles)
2.5
μ
s (2.5 cycles)
6.75
μ
s (27 cycles)
6.25
μ
s (25 cycles)
5.0
μ
s (5 cycles)
6.5
μ
s (13 cycles)
5.5
μ
s (11 cycles)
5.0
μ
s (5 cycles)
3.375
μ
s (13.5 cycles)
3.125
μ
s (12.5 cycles)
2.5
μ
s (2.5 cycles)
3.25
μ
s (6.5 cycles)
2.75
μ
s (5.5 cycles)
2.5
μ
s (2.5 cycles)
4
1
2
1
S
Slave address R/W
A
Data
A/A
P
A
Data
7 bits
“0”
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transnmits data to a slave-receiver
S
Slave address R/W
A
Data
A
P
A
Data
7 bits
“1”
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
7 bits
“0”
8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
1 to 8 bits
1 to 8 bits
S
R/W
A
Slave address
1st 7 bits
Slave address
2nd bytes
A
A
Data
Data
P
A/A
7 bits
“0”
8 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
7 bits
“1”
1 to 8 bits
1 to 8 bits
S
R/W
A
Slave address
1st 7 bits
Slave address
2nd bytes
A
Sr
Slave address
1st 7 bits
R/W
A
Data
Data
P
A
: Master to slave
: Slave to master
A
b7
b0
I
2
C START/STOP condition
control register
(S2D : address 0030
16
)
START/STOP condition set bit
SCL/SDA interrupt pin polarity
selection bit
0 : Falling edge active
1 : Rising edge active
SCL/SDA interrupt pin selection bit
0 : SDA valid
1 : SCL valid
Reserved
Do not write “1” to this bit.
SIS
SIP
SSC4 SSC3 SSC2 SSC1SSC0
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