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參數(shù)資料
| 型號： | M37510M7156FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 13/43頁 |
| 文件大?。?/td> | 614K |
| 代理商： | M37510M7156FP |
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13
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 7 Interrupt control
Fig. 8 Structure of interrupt-related registers
Interrupt disable flag (I)
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
b7
Interrupt edge selection register
(INTEDGE : address 003A
16
)
INT
0
active edge selection bit
INT
1
active edge selection bit
Not used (return “0” when read)
b0
0 : Falling edge active
1 : Rising edge active
b7
Interrupt request register 1
(IREQ1 : address 003C
16
)
INT
0
interrupt request bit
INT
1
interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
b0
b7
Interrupt request register 2
(IREQ2 : address 003D
16
)
Serial I/O2 receive interrupt request bit
Serial I/O2 transmit interrupt request bit
CNTR
0
interrupt request bit
CNTR
1
interrupt request bit
Timer 1 interrupt request bit
Key-on wake up interrupt request bit
Not used (return “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b0
b7
Interrupt control register 1
(ICON1 : address 003E
16
)
INT
0
interrupt enable bit
INT
1
interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
b0
b7
Interrupt control register 2
(ICON2 : address 003F
16
)
Serial I/O2 receive interrupt enable bit
Serial I/O2 transmit interrupt enable bit
CNTR
0
interrupt enable bit
CNTR
1
interrupt enable bit
Timer 1 interrupt enable bit
Key-on wake up interrupt enable bit
Not used (returns “0” when read)
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
b0
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