參數(shù)資料
型號(hào)： M37510M6
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 39/43頁
文件大?。?/td> 614K
代理商： M37510M6
39
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Symbol
t
w(RESET)
t
c(X
IN
)
t
wH(X
IN
)
t
wL(X
IN
)
t
c(CNTR)
t
wH(CNTR)
t
wH(INT)
t
wL(CNTR)
t
wL(INT)
t
c(S
CLK1
)
t
c(S
CLK2
)
t
wH(S
CLK1
)
t
wH(S
CLK2
)
t
wL(S
CLK1
)
t
wL(S
CLK2
)
t
su(R
X
D
1
–S
CLK1
)
t
su(R
X
D
2
–S
CLK2
)
t
h(S
CLK1
–R
X
D
1
)
t
h(S
CLK2
–R
X
D
2
)
TIMING REQUIREMENTS 1
(V
CC
= 4.0 to 5.5 V, V
SS
= 0 V, T
a
= –20 to 85
°
C, unless otherwise noted)
Parameter
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR
0
, CNTR
1
input cycle time
CNTR
0
, CNTR
1
input “H” pulse width
INT
0
, INT
1
input “H” pulse width
CNTR
0
, CNTR
1
input “L” pulse width
INT
0
, INT
1
input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O2 input set up time
Serial I/O1 input hold time
Serial I/O2 input hold time
Limits
Typ.
Min.
2
125
50
50
200
80
80
80
80
800
800
370
370
370
370
220
220
100
100
Max.
Unit
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
When f(
φ
) = 4 MHz and bit 6 of address 001A
16
or 0032
16
is “1” (clock synchronous). Divide this value by four when f(
φ
) = 4 MHz and bit 6 of address
001A
16
or 0032
16
is “0” (clock asynchronous).
Symbol
t
w(RESET)
c(X
IN
)
t
wH(X
IN
)
t
wL(X
IN
)
t
c(CNTR)
t
wH(CNTR)
t
wH(INT)
t
wL(CNTR)
t
wL(INT)
t
c(S
CLK1
)
t
c(S
CLK2
)
t
wH(S
CLK1
)
t
wH(S
CLK2
)
t
wL(S
CLK1
)
t
wL(S
CLK2
)
t
su(R
X
D
1
–S
CLK1
)
t
su(R
X
D
2
–S
CLK2
)
t
h(S
CLK1
–R
X
D
1
)
t
h(S
CLK2
–R
X
D
2
)
TIMING REQUIREMENTS 2
(V
CC
= 3.0 to 5.5 V, V
SS
= 0 V, T
a
= –20 to 85
°
C, unless otherwise noted)
Parameter
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR
0
, CNTR
1
input cycle time
CNTR
0
, CNTR
1
input “H” pulse width
INT
0
, INT
1
input “H” pulse width
CNTR
0
, CNTR
1
input “L” pulse width
INT
0
, INT
1
input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O2 input set up time
Serial I/O1 input hold time
Serial I/O2 input hold time
Limits
Typ.
Min.
2
500
200
200
500
230
230
230
230
2000
2000
950
950
950
950
400
400
200
200
Max.
Unit
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
When f(
φ
) = 1 MHz and bit 6 of address 001A
16
or 0032
16
is “1” (clock synchronous). Divide this value by four when f(
φ
) = 1 MHz and bit 6 of address
001A
16
or 0032
16
is “0” (clock asynchronous).
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