19
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 16 Structure of registers related to interrupts
b7
b0
Edge polarity selection register (EG : address 00D4
16
)
Interrupt control register 1 (ICON1: address 00FE
16
)
b7
b0
Interrupt control register 2 (ICON2: address 00FF
16
)
Interrupt request register 1 (IREQ1: address 00FC
16
)
Interrupt request register 2 (IREQ2: address 00FD
16
)
b7
b0
b7
b0
b7
b0
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
Bus arbitration interrupt enable bit
A-D conversion completion interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
Bus arbitration interrupt request bit
A-D conversion completion interrupt request bit
0 : No interrupt request
1 : Interrupt requested
INT
0
interrupt enable bit
INT
1
interrupt enable bit
CNTR
0
interrupt enable bit
CNTR
1
interrupt enable bit
0
: Interrupt disable
1
: Interrupt enable
INT
0
interrupt request bit
INT
1
interrupt request bit
CNTR
0
interrupt request bit
CNTR
1
interrupt request bit
0
: No interrupt request
1
: Interrupt request
INT
0
selection bit
0 : Falling edge
1 : Rising edge
INT
selection bit
0 : Falling edge
1 : Rising edge
CNTR
0
edge selection bit
0 : In event count mode, count rising edge.
: In pulse output mode, start at “H” level output.
: In pulse cycle measurement mode, measure a period from falling edge to falling edge.
: In pulse width measurement mode, measure an “H” period.
: In programmable one-shot output mode, generate one-shot “H” pulse after start at “L” output.
: Interrupt, falling edge active.
1 : In event count mode, count falling edge.
: In pulse output mode, start at “L” level output.
: In pulse cycle measurement mode, measure a period from rising edge to rising edge.
: In pulse width measurement mode, measure an “L” period.
: In programmable one-shot output mode, generate one-shot “L” pulse after start at “H” level output.
: Interrupt, rising edge active.
CNTR
1
edge selection bit
0 : In event count mode, count rising edge.
: In pulse output mode, start at “H” level output.
: In pulse cycle measurement mode, measure a period from falling edge to falling edge.
: In pulse width measurement mode, measure an “H” period.
: In programmable one-shot output mode, generate one-shot “H” pulse after start at “L” level output.
: Interrupt, falling edge active.
1 : In event count mode, count falling edge.
: In pulse output mode, start at “L” output.
: In pulse cycle measurement mode, measure a period from rising edge to rising edge.
: In pulse width measurement mode, measure an “L” period.
: In programmable one-shot output mode, generate one-shot “L” pulse after start at “H” output.
: Interrupt rising edge active.
INT
1
source selection bit at STP or WIT
0 : P3
1
/INT
1
1 : P0
0
– P0
7
“L” level (for key-on wake-up)
Not used (undefined at read)
Not used (undefined at read)
Not used (undefined at read)
0 : Interrupt disabled
1 : Interrupt enabled
Not used (undefined at read)
0 : No interrupt request
1 : Interrupt requested