參數(shù)資料
型號: M37481E8T
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機(jī)
文件頁數(shù): 18/97頁
文件大?。?/td> 1076K
代理商: M37481E8T
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
18
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 4. Interrupt vector addresses and priority
At reset
At detection of either rising edge or falling
edge of INT
0
input
At detection of either rising edge or falling
edge of INT
1
input
At input “L” to port P0 in key-on wake-up
mode
At detection of either rising edge or falling
edge of CNTR
0
input
At detection of either rising edge or falling
edge of CNTR
1
input
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At completion of serial I/O data reception
At completion of serial I/O transfer shift or
when transmission buffer is empty
At detection of bus collision
At completion of A-D conversion
At execution of BRK instruction
Non-maskable
External interrupt
(active edge programmable)
External interrupt
(active edge programmable)
Validity after execution of
STP/WIT instruction
External interrupt
(active edge programmable)
External interrupt
(active edge programmable)
Non-maskable software
interrupt
RESET (Note 2)
INT
0
INT
1
Key-on wake-up
CNTR
0
CNTR
1
Timer X
Timer Y
Timer 1
Timer 2
Serial I/O reception
Serial I/O transmission
Bus arbitration
A-D conversion
BRK instruction
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Interrupt source
Prior-
ity
Vector address (Note 1)
High-order Low-order
Interrupt request generating conditions
Remarks
FFFF
16
FFFD
16
FFFB
16
FFF9
16
FFF7
16
FFF5
16
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFE5
16
FFFE
16
FFFC
16
FFFA
16
FFF8
16
FFF6
16
FFF4
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
FFE4
16
Notes 1 :
Vector addresses contain interrupt jump destination addresses.
2 :
RESET is mentioned in the table because its operation is the same as an interrupt.
Fig. 15 Interrupt control diagram
Interrupt request bit
Interrupt enable bit
Interrupt disable flag
BRK instruction
Reset
Interrupt request
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