參數(shù)資料
型號(hào): M37480E8SP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù): 9/97頁(yè)
文件大?。?/td> 1076K
代理商: M37480E8SP
9
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
V
CC
, V
SS
AV
SS
V
REF
RESET
P0
0
– P0
7
P1
0
– P1
7
PIN DESCRIPTION
Table 3. Pin description
Clock input
Clock output
X
IN
X
OUT
Input
Output
Input
Input
I/O
I/O
Power source
Analog power
source input
Reference voltage
input
Reset input
I/O port P0
I/O port P1
P2
0
– P2
7
Apply a voltage of 2.7 to 5.5 V to V
CC
and 0 V to V
SS
.
Ground level input pin for A-D converter. Apply the same voltage as Vss. (This
pin is for 44P6N-A package only.)
Reference voltage input pin for A-D converter. (When the A-D converter is not
used, connect it to V
CC
.)
Reset input pin active “L”.
These are I/O pins for the internal clock generating circuit of the main clock. To
control the generating frequency, an external ceramic is connected between
the X
IN
and X
OUT
pins. If an external clock is used, the clock source should be
connected to the X
IN
pin, and the X
OUT
pin should be left open. The feedback
resistor is connected between X
IN
and X
OUT
.
8-bit I/O port. The output structure is CMOS output.
When this port is selected for input, pull-up transistors can be connected in
units of 1 bit, and a key-on wake-up function is provided.
8-bit I/O port. The output structure is CMOS output.
When this port is selected for input, pull-up transistors can be connected in
units of 4 bits. P1
2
and P1
3
are in common with timer output pins T
0
and T
1
.
, P1
5
, P1
6
and P1
7
are in common with serial I/O pins R
X
D, T
X
D, S
CLK
and
____
RDY
, respectively.
8-bit input port. (Only 4 bits of P2
0
to P2
3
for the 7480 group) or analog input
pins IN
0
to IN
7
(IN
0
to IN
3
for the 7480 group).
Input port P2
Input
4-bit input port. P3
0
and P3
1
can be configured to serve as external interrupt
input pins INT
0
and INT
1
.
4-bit I/O port. (2 bits of P4
0
and P4
1
for the 7480 group). The output structure
is N-channel open drain output, having a built-in clamp diode. P4
0
and P4
1
can
be configured to serve as timer I/O pins CNTR
0
and CNTR
1
.
4-bit I/O port. (This port is not included in the 7480 group.) The output structure
is N-channel open drain output, having built-in clamp diodes.
P3
0
– P3
3
Input port P3
P4
0
– P4
3
P5
0
– P5
3
I/O port P4
I/O port P5
I/O
I/O
Input
Pin
Name
Functions
Input/
output
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