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參數(shù)資料
| 型號(hào)： | M37477E8-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDSO32 |
| 封裝： | 0.450 INCH, 1.27 MM PITCH, PLASTIC, SOP-32 |
| 文件頁(yè)數(shù)： | 33/354頁(yè) |
| 文件大?。?/td> | 4508K |
| 代理商： | M37477E8-XXXFP |
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HARDWARE
1-111
7470/7471/7477/7478 GROUP USER’S MANUAL
1.13 Serial I/O
2
2 Receive operation of clock synchronous Serial I/O
The receive operation of the clock synchronous Serial I/O is described below.
q Start of receive operation
Receive operation begins by writing data into the Transmit buffer register (TB: address 00E016)
V2
in the receive enable state.
V1
Transmit data in the full-duplex data communication
Arbitrary dummy data in the half-duplex data communication
q Receive operation
1Receive data is input bit by bit from the P14/RxD pin to the Receive shift register in synchronization
with the rise of the synchronous clock.
2Receive data is input starting with the most significant bit of the Receive shift register. Each time
one bit is input, the contents of the Receive shift register are shifted by 1 in the direction of the
least significant bit.
3After one-byte data is completely input to the Receive shift register, the contents of the Receive
shift register are transferred to the receive buffer register (RB).
V3
4When receive data has been transferred to the receive buffer register, the receive buffer full flag
(b1) of the Serial I/O status register (SIOSTS) is set to “1,”
V4 so that a receive interrupt request
is generated.
V 1: Status in which the register for receive operation has been completed. Refer to “[Clock
synchronous Serial I/O receive setting method]” which will be described later.
V 2: When the external clock is selected, write data into the Transmit buffer register when the
synchronous clock is at “H.”
V 3: If receive data is further input to the Receive shift register when data remains (when the
receive buffer full flag is “1”) without reading out the contents of the Receive buffer register,
the overrun error flag of the Serial I/O status register is set to “1.” At this time, the data of the
Receive shift register is not transferred to the Receive buffer register and the original data of
the Receive buffer register is held.
V 4: The receive buffer full flag is cleared to “0” by reading out the Receive buffer register.
q
__________
When using the SRDY output
__________
At the time when data has been written into the Transmit buffer register, the level of the SRDY
__________
signal changes from “H” to “L” by which a receive ready state can be known externally. The SRDY
signal goes to “H” at the first fall of the synchronous clock of the synchronous clock.
q Receive interrupt operation (Serial I/O select only)
When receive data is transferred from the receive shift register to the Receive buffer register after
one-byte data is all input to the Receive shift register, an interrupt request is generated.
Figure 1.13B.4 shows a receive operation of the clock synchronous Serial I/O and Figure 1.13B.5
shows a receive timing chart of the clock synchronous Serial I/O.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37470M4-XXXSP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32 |
| M37477E8-XXXSP | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDIP32 |
| M37477M4-XXXSP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32 |
| M37477M8-XXXSP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32 |
| M37471M2-XXXSP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37477E8-XXXSP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 7470 SERIES |
| M37477E8-XXXSP/FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37477M2TXXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 7470 SERIES |
| M37477M2TXXXSP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 7470 SERIES |
| M37477M2TXXXSP/FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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