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參數(shù)資料
| 型號： | M37273E8SP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 8 Bits Microcomputer(8位單片機) |
| 中文描述： | 單芯片8位單片機（8位單片機） |
| 文件頁數(shù)： | 52/138頁 |
| 文件大?。?/td> | 1327K |
| 代理商： | M37273E8SP |
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52
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
8.10.2 Clamping Circuit and Low-pass Filter
The clamp circuit clamps the sync chip part of the composite video
signal input from the CV
IN
pin. The low-pass filter attenuates the noise
of clamped composite video signal. The CV
IN
pin to which composite
video signal is input requires a capacitor (0.1
μ
F) coupling outside.
Pull down the CV
IN
pin with a resistor of hundreds of kiloohms to 1
M
. In addition, we recommend to install externally a simple low-
pass filter using a resistor and a capacitor at the CV
IN
pin (refer to
Figure 8.10.1).
8.10.3 Sync Slice Circuit
This circuit takes out a composite sync signal from the output signal
of the low-pass filter.
8.10.4 Synchronous Signal Separation Circuit
This circuit separates a horizontal synchronous signal and a vertical
synchronous signal from the composite sync signal taken out in the
sync slice circuit.
(1)Horizontal Synchronous Signal (H
sep
)
A one-shot horizontal synchronizing signal Hsep is generated at
the falling edge of the composite sync signal.
(2)Vertical Synchronous Signal (V
sep
)
As a V
sep
signal generating method, it is possible to select one of
the following 2 methods by using bit 4 of the data slicer control
register 2 (address 00E1
16
).
Method 1
The LOW level width of the composite sync signal is
measured. If this width exceeds a certain time, a V
sep
signal is generated in synchronization with the rising
of the timing signal immediately after this LOW level.
Method 2
The LOW level width of the composite sync signal is
measured. If this width exceeds a certain time, it is
detected whether a falling of the composite sync sig-
nal exits or not in the LOW level period of the timing
signal immediately after this LOW level. If a falling
exists, a V
sep
signal is generated in synchronization
with the rising of the timing signal (refer to Figure
8.10.6).
Figure 8.10.6 shows a V
sep
generating timing. The timing signal shown
in the figure is generated from the reference clock which the timing
generating circuit outputs.
Reading bit 5 of data slicer control register 2 permits determinating
the shape of the V-pulse portion of the composite sync signal. As
shown in Figure 8.10.7, when the A level matches the B level, this bit
is “0.” In the case of a mismatch, the bit is “1.”
Fig. 8.10.6 Vsep Generating Timing (method 2)
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| M37273EFSP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
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