參數(shù)資料
型號: M37273E8SP
廠商: Mitsubishi Electric Corporation
英文描述: Single Chip 8 Bits Microcomputer(8位單片機)
中文描述: 單芯片8位單片機(8位單片機)
文件頁數(shù): 30/138頁
文件大小: 1327K
代理商: M37273E8SP
30
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
8.6.1 I
2
C Data Shift Register
The I
2
C data shift register (S0 : address 00F6
16
) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to the
outside from bit 7 in synchronization with the SCL clock, and each
time one-bit data is output, the data of this register are shifted one bit
to the left. When data is received, it is input to this register from bit 0
in synchronization with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.
The I
2
C data shift register is in a write enable status only when the
ESO bit of the I
2
C control register (address 00F9
16
) is “1.” The bit
counter is reset by a write instruction to the I
2
C data shift register.
When both the ESO bit and the MST bit of the I
2
C status register
(address 00F8
16
) are “1,” the SCL is output by a write instruction to
the I
2
C data shift register. Reading data from the I
2
C data shift regis-
ter is always enabled regardless of the ESO bit value.
Note:
To write data into the I
2
C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
Fig. 8.6.2 Data Shift Register
7 b
6 b
5 b
4 b
3 b
2 b
1 b
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相關(guān)PDF資料
PDF描述
M37273EFSP Single Chip 8 Bits Microcomputer(8位單片機)
M37273M8 Single Chip 8 Bits Microcomputer(8位單片機)
M37273MF Single Chip 8 Bits Microcomputer(8位單片機)
M372F3200DJ3-C 32M x 72 DRAM DIMM with ECC Using 16Mx4, 4K & 8K Refresh, 3.3V
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