參數(shù)資料
型號: M37272M8H
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述: 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù): 30/131頁
文件大?。?/td> 1297K
代理商: M37272M8H
30
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6H/M8H/MAH/MFH–XXXSP/FP
M37272E8SP/FP, M37272EFSP/FP
MITSUBISHI MICROCOMPUTERS
Rev 1.0
8.6.1 I
2
C Data Shift Register
The I
2
C data shift register (S0 : address 00F6
16
) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to the
outside from bit 7 in synchronization with the SCL clock, and each
time one-bit data is output, the data of this register are shifted one bit
to the left. When data is received, it is input to this register from bit 0
in synchronization with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.
The I
2
C data shift register is in a write enable status only when the
ESO bit of the I
2
C control register (address 00F9
16
) is “1.” The bit
counter is reset by a write instruction to the I
2
C data shift register.
When both the ESO bit and the MST bit of the I
2
C status register
(address 00F8
16
) are “1,” the SCL is output by a write instruction to
the I
2
C data shift register. Reading data from the I
2
C data shift regis-
ter is always enabled regardless of the ESO bit value.
Note:
To write data into the I
2
C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
Fig. 8.6.2 Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
I C data shift register1(S0) [Address 00F6
16
]
B
Functions
After reset
R W
I
C
D
a
t
a
S
h
i
f
t
R
e
g
i
s
t
e
r
0
to
7
T
r
h
e
i
s
e
i
i
v
s
a
n
d
8
t
-
b
i
t
n
s
d
h
i
f
t
r
i
r
t
e
e
g
i
r
s
a
t
e
n
r
s
m
t
o
t
s
t
o
a
r
t
e
a
.
c
e
a
a
a
w
t
i
d
Indeterminate
N
o
t
e
:
To write data into the I C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
Name
D
0
t
o
D
7
R W
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