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參數(shù)資料
| 型號： | M37272M8H |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| 中文描述： | 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器 |
| 文件頁數(shù)： | 108/131頁 |
| 文件大?。?/td> | 1297K |
| 代理商： | M37272M8H |
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108
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6H/M8H/MAH/MFH
–
XXXSP/FP
M37272E8SP/FP, M37272EFSP/FP
MITSUBISHI MICROCOMPUTERS
Rev 1.0
F0
16
F
F2
16
F
F
F5
16
F
F7
16
F
F
FA
16
F
F
FD
16
F
1
1
6
3
1
4
1
6
6
6
1
6
8
1
9
1
6
6
B
1
C
1
6
6
E
1
F
1
6
6
E0
16
E
E2
16
E
E
E5
16
E6
16
E7
16
E8
16
E
E
1
1
6
3
1
4
1
6
6
9
1
A
1
6
EB
16
E
ED
16
E
F
1
C
1
6
E
1
6
6
6
Address
Serial I/O register (SIO)
Serial I/O mode register (SM)
A
A-D control register 2 (AD2)
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
A
D
1
)
T
Timer 6 (T6)
T
m
e
r
T
m
e
r
Timer 3 (T3)
T
m
e
r
T
m
e
r
T
m
e
r
I
2
C data shift register (S0)
I
2
C
a
d
d
r
e
s
s
r
i
m
e
r
5
(
T
5
)
i
i
1
2
(
(
T
T
1
2
)
)
C
Caption data register 2 (CD2)
a
p
t
i
o
n
d
a
t
a
r
e
g
i
s
t
e
r
1
(
C
D
1
)
C
D
Data slicer test register 1
S
n
c
h
r
o
n
o
u
s
a
a
p
t
t
i
o
s
n
l
i
c
p
e
o
r
s
t
i
e
t
i
s
o
t
n
e
r
e
g
g
i
s
i
s
t
e
t
e
r
r
2
(
C
P
S
)
a
r
C
Data clock position register (DPS)
l
o
c
k
r
u
n
-
i
n
d
e
t
e
c
t
r
e
g
i
s
t
e
r
(
C
R
D
)
Register
D
D
a
a
t
t
a
a
s
s
l
l
i
i
c
c
e
e
r
r
c
c
o
o
n
n
t
t
r
r
o
o
l
l
r
r
e
e
g
g
i
i
s
s
t
t
e
e
r
r
1
2
(
(
D
D
S
S
C
C
1
2
)
)
i
i
i
4
m
m
(
o
o
T
d
d
4
e
e
)
r
r
e
e
g
g
i
i
s
s
t
t
e
e
r
r
1
2
(
(
T
T
M
M
1
2
)
)
I
2
C
I
2
C
C
U
c
c
o
l
o
m
n
c
t
r
k
d
o
l
o
r
e
n
r
e
g
t
r
g
i
o
i
s
t
l
e
r
t
e
r
e
r
g
(
S
i
s
(
C
1
t
P
D
e
)
c
e
r
U
(
M
S
2
)
)
In
In
Interrupt control register 1 (ICON1)
In
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
t
t
e
e
r
r
r
r
u
u
p
p
t
t
r
r
e
e
q
q
u
u
e
e
s
s
t
t
r
r
e
e
g
g
i
i
s
s
t
t
e
e
r
r
1
2
(
(
I
I
R
R
E
E
Q
Q
1
2
)
)
g
i
s
t
e
r
2
(
I
C
O
N
2
)
y
s
i
g
n
a
l
c
o
u
n
t
e
r
r
e
g
i
s
t
e
r
(
H
C
)
P
o
s
b
7
b0
Bit allocation
State immediately after reset
b7
b
0
I
S
F
R
1
A
r
e
a
(
a
d
d
r
e
s
s
e
s
E
0
1
6
t
o
F
F
1
6
)
I
2
C status register (S1)
e
g
i
s
t
e
r
(
S
0
D
)
:
:
“
“
0
”
i
m
m
e
d
i
a
t
e
l
y
a
f
t
e
r
r
e
s
e
t
:
I
n
a
d
t
e
e
t
e
r
r
m
s
i
n
t
a
t
e
i
m
m
e
d
i
a
t
e
l
y
f
r
e
e
0
1
<State immediately after reset>
1
”
i
m
m
e
d
i
a
t
e
l
y
a
f
t
e
r
r
e
s
e
t
: Fix this bit to
“
0
”
(do not write
“
1
”
)
:
<Bit allocation>
F
u
n
c
t
i
o
n
b
i
t
:
N
o
f
u
n
c
t
i
o
n
b
i
t
: Fix this bit to
“
1
”
(do not write
“
0
”
)
N
a
m
e
:
1
0
TM20
0
T
M
2
1
TM22
TM23
TM24
TM10
T
M
1
1
TM12
TM13
TM14
CM2
TM1R
TM2R
TM3R
1
M
1
TM4R
OSDR
IN
VSCR
IN3R
2
IN1R
DSR
M
S
R
TM1E
T
2
E
T
3
E
TM4E
O
IN
S
D
E
V
S
C
E
IN1E
DSE
S
E
2
E
T
M
2
5
00
16
00
16
07
16
FF
16
0
F
1
6
7
1
0
1
6
07
16
T
M
1
5
TM16
T
M
M
1
7
TM26
T
2
7
S
A
D
0
S
A
A
D
1
SAD2
L
S
A
D
3
SAD4
S
R
A
D
5
S
A
D
6
RBW
LRB
AD0
S
A
PIN
BB
T
X
M
S
S
T
BC0
BC1
BC2
ESO
ALS
BSEL0
C
B
I
B
E
L
1
CCR0
0
CCR1
0
CCR2
CCR3
1
CCR4
1
ACK
1
0
1
6
0
00
16
3
0
1
C
1
6
CKR
R
IICR
TM56R
IN
3
E
CKE
IICE
TM56E
TM56C
CM7
C
M
5
CM6
SM0
SM1
S
M
2
SM3
ADC10
D
C
ADC11
D
C
2
ADC12
D
C
ADC14
A
2
0
A
2
1
A
2
A
D
C
2
5
SM5
S
M
6
ADC24ADC23
1
0
S
FAST
MODE
B
A
I
D
T
0
0
1
9
1
6
00
16
0
1
6
F
1
6
DSC10
DSC11
1
D
L
DSC12
DSC20
D
L
DSC23
DSC24
D
D
S
C
2
5
CRD3
CRD4
CRD5
C
R
D
6
C
R
D
7
DPS3
DPS4
DPS5
P
DPS6
DPS7
P
CPS0
CPS3
CPS4
C
S
5
C
P
S
1
C
P
S
2
CPS6
C
S
7
HC0
HC3
H
C
4
H
C
5
H
C
1
H
C
2
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
6
C
D
H
1
0
C
D
H
1
3
C
D
H
1
4
CDH15
6
C
D
H
1
1
CDH12
C
D
H
1
C
D
H
1
7
C
1
0
CDL13
CDL14
C
L
1
5
C
1
1
CDL12
C
D
L
1
6
C
D
L
1
7
00
16
0
1
6
0
1
6
00
16
6
00
16
00
16
0
1
6
0
1
6
D
1
D2
D
3
D
4
D5
D
6
D7
D
0
0
0
0
0
0
0
0
0
0
0
0
A
K
T
6
6
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