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    參數(shù)資料
    型號: M37272M8-526SP
    廠商: Mitsubishi Electric Corporation
    英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
    中文描述: 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
    文件頁數(shù): 56/131頁
    文件大小: 1297K
    代理商: M37272M8-526SP
    56
    SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
    and ON-SCREEN DISPLAY CONTROLLER
    M37272M6H/M8H/MAH/MFH
    XXXSP/FP
    M37272E8SP/FP, M37272EFSP/FP
    MITSUBISHI MICROCOMPUTERS
    Rev 1.0
    8.10.7 Reference Voltage Generating Circuit
    and Comparator
    The composite video signal clamped by the clamping circuit is input
    to the reference voltage generating circuit and the comparator.
    (1) Reference voltage generating circuit
    This circuit generates a reference voltage (slice voltage) by us-
    ing the amplitude of the clock run-in pulse in line specified by the
    data slice line specification circuit. Connect a capacitor between
    the V
    HOLD
    pin and the V
    SS
    pin, and make the length of wiring as
    short as possible so that a leakage current may not be gener-
    ated.
    (2) Comparator
    The comparator compares the voltage of the composite video
    signal with the voltage (reference voltage) generated in the refer-
    ence voltage generating circuit, and converts the composite video
    signal into a digital value.
    Fig. 8.10.10 Clock Run-in Detect Register
    8.10.8 Start Bit Detecting Circuit
    This circuit detects a start bit at line decided in the data slice line
    specification circuit.
    The detection of a start bit is described below.
    A sampling clock is generated by dividing the reference clock out-
    put by the timing signal.
    A clock run-in pulse is detected by the sampling clock.
    After detection of the pulse, a start bit pattern is detected from the
    comparator output.
    8.10.9 Clock Run-in Determination Circuit
    This circuit determinates clock run-in by counting the number of pulses
    in a window of the composite video signal.
    The reference clock count value in one pulse cycle is stored in bits 3
    to 7 of the clock run-in detect register (address 00E4
    16
    ). Read out
    these bits after the occurrence of a data slicer interrupt (refer to
    “8.10.12 Interrupt Request Generating Circuit”).
    Figure 8.10.10 shows the structure of clock run-in detect register.
    b7 b6 b5 b4 b3 b2 b1 b0
    Clock run-in detect register (CRD) [Address 00E4
    16
    ]
    R W
    Clock Run-in Detect Register
    0
    to
    2
    3
    to
    7
    0
    R
    Test bits
    Number of reference clocks to
    be counted in one clock run-in
    pulse period.
    Clock run-in detection bit
    (CRD3 to CRD7)
    0
    R
    Read-only
    B
    After reset
    Functions
    Name
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