參數(shù)資料
型號: M37272M8-526SP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述: 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù): 20/131頁
文件大小: 1297K
代理商: M37272M8-526SP
20
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6H/M8H/MAH/MFH
XXXSP/FP
M37272E8SP/FP, M37272EFSP/FP
MITSUBISHI MICROCOMPUTERS
Rev 1.0
Fig. 8.3.2 Interrupt Request Register 1
Fig. 8.3.3 Interrupt Request Register 2
b7b
6 b
5b4b
3 b
2b
1b
0
Interrupt request register 1 (IREQ1) [Address 00FC
16
]
B
0
Name
F
n
r
r
i
n
e
r
o
i
n
t
e
N
o
I
n
t
e
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
u
t
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t
r
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t
r
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t
t
i
p
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p
e
p
e
p
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n
t
q
t
q
t
q
t
q
s
e
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u
r
e
u
r
e
u
A
f
t
e
r
r
e
s
e
t
R W
R
Interrupt Request Register 1
0
1
0
1
0
1
0
1
:
:
:
:
:
:
:
:
N
I
n
N
I
n
N
I
o
t
o
t
i
e
u
r
u
r
u
r
u
r
r
q
s
q
s
q
s
q
s
u
t
u
t
u
t
u
t
e
i
e
i
e
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i
s
s
s
s
s
s
s
s
t
u
t
s
u
t
s
u
t
s
u
i
s
e
s
e
s
e
s
e
s
d
s
d
s
d
s
d
u
e
d
e
e
s
Timer 1 interrupt
request bit (TM1R)
Timer 2 interrupt
request bit (TM2R)
T
m
e
r
3
i
n
t
r
e
q
u
e
s
t
b
i
t
T
m
e
r
4
i
n
t
r
e
q
u
e
s
t
b
i
t
OSD interrupt request
bit (OSDR)
V
SYNC
interrupt
request bit (VSCR)
IN
T
3
e
x
t
e
r
n
r
e
q
u
e
s
t
b
i
t
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
1
2
i
e
e
r
r
r
r
u
(
u
(
p
T
p
T
t
M
t
M
3
R
)
3
i
4
R
)
4
5
6
a
l
(
i
n
V
t
S
e
r
r
u
R
p
)
t
C
7
i
u
e
d
e
i
u
e
d
e
i
u
e
d
e
0
0
0
0
0
0
0
0
: “0” can be set by software, but “1” cannot be set.
R
R
R
R
R
R
R
0
7 b
6b
5b
4b
3 b
2b
1b
0
In
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
2
(
I
R
E
Q
2
)
[
A
d
d
r
e
s
s
0
0
F
D
B
0
N
t
b
c
t
b
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r
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a
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I
n
(
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t
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R W
In
t
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r
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e
q
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t
R
e
g
i
s
t
e
r
2
IN
r
e
D
r
e
Serial I/O interrupt
request bit (S1R)
f(X
IN
)/4096 interrupt
request bit (CKR)
T
q
1
u
t
a
q
u
e
s
s
s
x
t
l
i
e
l
N
t
e
D
i
n
I
r
S
t
e
)
u
r
r
u
p
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e
e
R
r
R
0
1
0
1
0
1
0
1
:
:
:
:
:
:
:
:
N
I
n
N
I
n
N
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d
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d
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e
s
t
s
1
a
i
p
)
t
2
3
4
INT2 external interrupt
request bit (IN2R)
Multi-master I
2
C-BUS
interrupt request bit (IICR)
Timer 5 6 interrupt
request bit (TM56R)
5
7
Fix this bit to “0.”
0
u
e
d
e
0
1
0
1
0
1
:
:
:
:
:
:
N
I
n
N
I
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N
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d
s
d
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d
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s
:
0
c
a
n
b
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s
e
t
b
y
s
o
f
t
w
a
r
e
,
b
u
t
1
c
a
n
n
o
t
b
e
s
e
t
.
0
0
0
0
0
0
i
u
e
d
e
1
6
]
R
R
R
R
R
R
R W
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d
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d
r
6
r
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d
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p
0
R
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