- 您現(xiàn)在的位置：買(mǎi)賣IC網(wǎng) > PDF目錄370842 > M37272M8-183SP (Mitsubishi Electric Corporation) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER PDF資料下載
參數(shù)資料
| 型號(hào)： | M37272M8-183SP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| 中文描述： | 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器 |
| 文件頁(yè)數(shù)： | 35/131頁(yè) |
| 文件大?。?/td> | 1297K |
| 代理商： | M37272M8-183SP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)當(dāng)前第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)
35
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6H/M8H/MAH/MFH
–
XXXSP/FP
M37272E8SP/FP, M37272EFSP/FP
MITSUBISHI MICROCOMPUTERS
Rev 1.0
8.6.5 I
2
C Status Register
The I
2
C status register (address 00F8
16
) controls the I
2
C-BUS inter-
face status. The low-order 4 bits are read-only bits and the high-
order 4 bits can be read out and written to.
(1) Bit 0: last receive bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an ACK
clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is
set to “1.” Except in the ACK mode, the last bit value of received data
is input. The state of this bit is changed from “1” to “0” by executing a
write instruction to the I
2
C data shift register (address 00F6
16
).
(2) Bit 1: general call detecting flag (AD0)
This bit is set to “1” when a general call
whose address data is all
“0” is received in the slave mode. By a general call of the master
device, every slave device receives control data after the general
call. The AD0 bit is set to “0” by detecting the STOP condition or
START condition.
General call: The master transmits the general call address “00
16
”
to all slaves.
(3) Bit 2: slave address comparison flag (AAS)
This flag indicates a comparison result of address data.
I
In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions.
The address data immediately after occurrence of a START con-
dition matches the slave address stored in the high-order 7 bits
of the I
2
C address register (address 00F7
16
).
A general call is received.
I
In the slave reception mode, when the 10-bit addressing format is
selected, this bit is set to “1” with the following condition.
When the address data is compared with the I
2
C address regis-
ter (8 bits consists of slave address and RBW), the first bytes
match.
I
The state of this bit is changed from “1” to “0” by executing a write
instruction to the I
2
C data shift register (address 00F6
16
).
(4) Bit 3: arbitration lost
detecting flag (AL)
n the master transmission mode, when a device other than the mi-
crocomputer sets the SDA to “L,”, arbitration is judged to have been
lost, so that this bit is set to “1.” At the same time, the TRX bit is set to
“0,” so that immediately after transmission of the byte whose arbitra-
tion was lost is completed, the MST bit is set to “0.” When arbitration
is lost during slave address transmission, the TRX bit is set to “0” and
the reception mode is set. Consequently, it becomes possible to re-
ceive and recognize its own slave address transmitted by another
master device.
Arbitration lost: The status in which communication as a master is
disabled.
(5) Bit 4: I
2
C-BUS interface interrupt request bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte data
is transmitted, the state of the PIN bit changes from “1” to “0.” At the
same time, an interrupt request signal is sent to the CPU. The PIN bit
is set to “0” in synchronization with a falling edge of the last clock
(including the ACK clock) of an internal clock and an interrupt re-
quest signal occurs in synchronization with a falling edge of the PIN
bit. When detecting the STOP condition in slave, the multi-master
I
2
C-BUS interface interrupt request bit (IR) is set to “1” (interrupt re-
quest) regardless of falling of PIN bit. When the PIN bit is “0,” the
SCL is kept in the “0” state and clock generation is disabled. Figure
8.6.8 shows an interrupt request signal generating timing chart.
The PIN bit is set to “1” in any one of the following conditions.
Writing “1” to the PIN bit
Executing a write instruction to the I
2
C data shift register (address
00F6
16
). (See note)
When the ESO bit is “0”
At reset
Note:
It takes 8 BCLK cycles or more until PIN bit becomes “1” after write
instructions are executed to these registers.
The conditions in which the PIN bit is set to “0” are shown below:
Immediately after completion of 1-byte data transmission (includ-
ing when arbitration lost is detected)
Immediately after completion of 1-byte data reception
In the slave reception mode, with ALS = “0” and immediately after
completion of slave address or general call address reception
In the slave reception mode, with ALS = “1” and immediately after
completion of address data reception
(6) Bit 5: bus busy flag (BB)
This bit indicates the status of use of the bus system. When this bit is
set to “0,” this bus system is not busy and a START condition can be
generated. When this bit is set to “1,” this bus system is busy and the
occurrence of a START condition is disabled by the START condition
duplication prevention function (See note).
This flag can be written by software only in the master transmission
mode. In the other modes, this bit is set to “1” by detecting a START
condition and set to “0” by detecting a STOP condition. When the
ESO bit of the I
2
C control register (address 00F9
16
) is “0” and at
reset, the BB flag is kept in the “0” state.
(7) Bit 6: communication mode specification bit
(transfer direction specification bit: TRX)
This bit decides the direction of transfer for data communication. When
this bit is “0,” the reception mode is selected and the data of a trans-
mitting device is received. When the bit is “1,” the transmission mode
is selected and address data and control data are output into the
SDA in synchronization with the clock generated on the SCL.
When the ALS bit of the I
2
C control register (address 00F9
16
) is “0” in
the slave reception mode is selected, the TRX bit is set to “1” (trans-
mit) if the least significant bit (R/W bit) of the address data transmit-
ted by the master is “1.” When the ALS bit is “0” and the R/W bit is
“0,” the TRX bit is cleared to “0” (receive).
The TRX bit is cleared to “0” in one of the following conditions.
When arbitration lost is detected.
When a STOP condition is detected.
When occurence of a START condition is disabled by the START
condition duplication prevention function (Note).
With MST = “0” and when a START condition is detected.
With MST = “0” and when ACK non-return is detected.
At reset
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37272M8-184SP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37272MA-052SP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37272MA-055SP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37272MA-309SP | Silver Mica Capacitor; Capacitance:10pF; Capacitance Tolerance: 0.5pF; Series:CM04; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:3.6mm; Leaded Process Compatible:No RoHS Compliant: No |
| M37274EFSP | CONN HEADER 14POS SGL PCB 30GOLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37272M8-184SP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37272M8400SP | 制造商:MITSUBISHI 功能描述:* |
| M37272M8500SP | 制造商:MITSUBISHI 功能描述:* |
| M37272M8-517SP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37272M8-526SP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。