參數(shù)資料
型號： M37272M8-122SP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù)： 40/131頁
文件大?。?/td> 1297K
代理商： M37272M8-122SP
40
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6H/M8H/MAH/MFH
–
XXXSP/FP
M37272E8SP/FP, M37272EFSP/FP
MITSUBISHI MICROCOMPUTERS
Rev 1.0
Fig. 8.6.12 Address Data Communication Format
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“
0
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1
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8
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a
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1 to 8 bits
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1 to 8 bits
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(1
)
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Slave address
1st 7 bits
b
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
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(2
)
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Slave address
2nd byte
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1 to 8 bits
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Slave address
1st 7 bits
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A
7 bits
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“
0
”
c
e
8 bits
a
s
7 bits
-
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Slave address
2nd byte
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1 to 8 bits
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r
Slave address
1st 7 bits
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1 to 8 bits
“
1
”
(4
)
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A : A
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From master to slave
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8.6.12 Precautions when using multi-master
I
2
C-BUS interface
(1) Read-modify-write instruction
The precautions when the raead-modify-write instruction such as SEB,
CLB etc. is executed for each register of the multi-master I
2
C-BUS
interface are described below.
I
2
C data shift register (S0)
When executing the read-modify-write instruction for this register
during transfer, data may become a value not intended.
I
2
C address register (S0D)
When the read-modify-write instruction is executed for this register
at detecting the STOP condition, data may become a value not
intended. It is because hardware changes the read/write bit (RBW)
at the above timing.
I
2
C status register (S1)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by hardware.
I
2
C control register (S1D)
When the read-modify-write instruction is executed for this register
at detecting the START condition or at completing the byte transfer,
data may become a value not intended. Because hardware changes
the bit counter (BC0–BC2) at the above timing.
I
2
C clock control register (S2)
The read-modify-write instruction can be executed for this register.
(2) START condition generating procedure us-
ing multi-master
Procedure example (The necessary conditions of the generating
procedure are described as the following
to
).
—
LDA
SEI
BBS 5,S1,BUSBUSY
BUSFREE:
STA S0
LDM #$F0, S1
CLI
(Taking out of slave address value)
(Interrupt disabled)
(BB flag confirming and branch process)
(Writing of slave address value)
(Trigger of START condition generating)
(Interrupt enabled)
BUSBUSY:
CLI
(Interrupt enabled)
Use “STA,” “STX” or “STY” of the zero page addressing instruction
for writing the slave address value to the I
2
C data shift register.
Use “LDM” instruction for setting trigger of START condition gener-
ating.
Write the slave address value of above
and set trigger of START
condition generating of above
continuously shown the above
procedure example.
Disable interrupts during the following three process steps:
BB flag confirming
Writing of slave address value
Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.
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