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參數(shù)資料
| 型號： | M37272M8-122SP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| 中文描述： | 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器 |
| 文件頁數(shù)： | 37/131頁 |
| 文件大?。?/td> | 1297K |
| 代理商： | M37272M8-122SP |
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37
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6H/M8H/MAH/MFH
–
XXXSP/FP
M37272E8SP/FP, M37272EFSP/FP
MITSUBISHI MICROCOMPUTERS
Rev 1.0
8.6.6 START Condition Generation Method
When the ESO bit of the I
2
C control register (address 00F9
16
) is “1,”
execute a write instruction to the I
2
C status register (address 00F8
16
)
to set the MST, TRX and BB bits to “1.” A START condition will then
be generated. After that, the bit counter becomes “000
2
” and an SCL
for 1 byte is output. The START condition generation timing and BB
bit set timing are different in the standard clock mode and the high-
speed clock mode. Refer to Figure 8.6.9 for the START condition
generation timing diagram, and Table 8.6.2 for the START condition/
STOP condition generation timing table.
Fig. 8.6.9 START Condition Generation Timing Diagram
I
2
C status register
write signal
Hold time
S
e
t
t
u
e
p
i
m
SCL
SDA
BB flag
S
o
e
r
t
B
t
B
i
m
f
e
l
a
g
f
8.6.7 STOP Condition Generation Method
When the ESO bit of the I
2
C control register (address 00F9
16
) is “1,”
execute a write instruction to the I
2
C status register (address 00F8
16
)
for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A
STOP condition will then be generated. The STOP condition genera-
tion timing and the BB flag reset timing are different in the standard
clock mode and the high-speed clock mode. Refer to Figure 8.6.10
for the STOP condition generation timing diagram, and Table 8.6.2
for the START condition/STOP condition generation timing table.
Fig. 8.6.10 STOP Condition Generation Timing Diagram
Table 8.6.2 START Condition/STOP Condition Generation Tim-
ing Table
Item
Setup time
(START condition)
Setup time
(STOP condition)
Hold time
Set/reset time
for BB flag
Standard Clock Mode
5.0
μ
s (20 cycles)
4.25
μ
s (17 cycles)
5.0
μ
s (20 cycles)
3.0
μ
s (12 cycles)
High-speed Clock Mode
2.5
μ
s (10 cycles)
1.75
μ
s (7 cycles)
2.5
μ
s (10 cycles)
1.5
μ
s (6 cycles)
Note:
Absolute time at
φ
= 4 MHz. The value in parentheses denotes the
number of
φ
cycles.
I
2
C
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o
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d
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S
e
t
t
u
e
p
i
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SCL
D
B
S
A
f
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a
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R
se
B
t
B
t
i
f
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l
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g
r
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