參數(shù)資料
型號: M37272M8-062FP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述: 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù): 21/131頁
文件大?。?/td> 1297K
代理商: M37272M8-062FP
21
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6H/M8H/MAH/MFH
XXXSP/FP
M37272E8SP/FP, M37272EFSP/FP
MITSUBISHI MICROCOMPUTERS
Rev 1.0
Fig. 8.3.4 Interrupt Control Register 1
7b
6 b5b
4b
3 b2b
1b
0
In
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
I
C
O
N
1
)
[
A
d
d
r
e
s
s
0
0
F
E
1
6
]
B
0
N
i
b
i
b
3
e
r
4
b
l
e
a
n
i
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n
i
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t
e
(
t
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t
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r
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r
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r
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r
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T
Functions
n
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r
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:
I
n
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r
r
:
I
n
t
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r
1
:
I
n
t
e
r
0
:
I
n
t
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r
1
:
I
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r
A
f
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r
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s
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t
R W
R W
In
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R
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g
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r
1
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i
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1
2
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1
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4
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t
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t
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a
)
0
1
0
1
0
:
:
:
I
p
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p
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1
i
a
)
2
i
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(
)
3
4
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(
O
V
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b
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n
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S
D
D
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3
a
b
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)
i
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b
l
e
b
i
t
u
u
u
u
u
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r
r
r
r
0
1
0
1
0 : Interrupt disabled
1 : Interrupt enabled
:
:
:
:
I
I
I
I
n
n
n
n
t
t
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t
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e
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e
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p
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a
b
b
b
b
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e
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e
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d
d
d
d
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0
0
0
0
0
0
R W
R W
R W
R W
R —
7
Nothing is assigned. This bit is a write disable
bit. When this bit is read out, the value is “0.”
i
a
(
)
5
Y
T
N
(
n
t
E
e
i
t
e
r
)
n
(
r
u
p
t
e
n
a
b
l
e
t
S
e
e
0
R W
6
t
r
a
I
N
l
i
3
n
E
t
e
)
r
r
u
p
t
l
0
R W
Fig. 8.3.5 Interrupt Control Register 2
b7b6 b5b4b3 b2b1b0
In
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
(
I
C
O
N
2
)
[
A
d
d
r
e
s
s
0
0
F
F
1
6
]
B
0
N
t
b
i
c
b
I
/
O
e
b
/
4
0
l
e
a
r
t
e
i
t
i
t
9
i
t
m
n
(
r
(
i
n
(
6
(
e
a
I
N
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C
F
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n
c
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i
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n
s
A
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t
R W
R W
In
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r
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p
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C
o
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t
r
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l
R
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g
i
s
t
e
r
2
IN
e
D
e
S
e
f(
e
T
a
t
a
r
a
1
b
a
b
i
a
b
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)
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b
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u
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r
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t
e
)
u
)
p
)
r
u
)
r
r
u
p
t
n
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
1
a
n
e
n
X
I
n
i
t
p
t
2
t
3
4
IN
e
M
i
n
b
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a
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t
m
n
a
2
b
t
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r
(
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e
b
l
-
f
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m
a
C
r
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x
t
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s
)
b
r
t
n
n
(
e
t
a
I
N
r
e
l
2
I
2
C
r
r
u
i
n
E
t
)
-
p
e
r
r
u
p
t
n
b
a
e
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
0
R W
R W
R W
R W
p
t
b
5
l
B
t
U
e
S
n
b
c
E
5
i
a
l
e
i
0
R W
6
i
t
6
T
i
n
M
t
e
5
r
r
6
u
E
p
)
t
i
(
0 : Interrupt disabled
1 : Interrupt enabled
0
R W
7
T
m
w
e
t
c
r
h
5
b
i
6
(
T
i
n
M
t
e
5
r
6
r
u
C
p
)
t
i
t
0 : Timer 5
1 : Timer 6
0
R W
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