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參數資料
| 型號： | M37272M8-062FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| 中文描述： | 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器 |
| 文件頁數： | 15/131頁 |
| 文件大?。?/td> | 1297K |
| 代理商： | M37272M8-062FP |
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15
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6H/M8H/MAH/MFH
–
XXXSP/FP
M37272E8SP/FP, M37272EFSP/FP
MITSUBISHI MICROCOMPUTERS
Rev 1.0
Fig. 8.2.4 Memory Map of Special Function Register 1 (SFR1) (2)
F
F
F2
16
F3
16
F
F
F
F
F
F
FA
16
F
FC
16
F
FE
16
0
1
1
1
6
6
4
1
5
1
6
1
7
1
8
1
9
1
6
6
6
6
6
6
B
1
6
D
1
6
F
1
6
E
E
E
E3
16
E
E
E
E7
16
E8
16
E
E
0
1
1
1
2
1
6
6
6
4
1
5
1
6
1
6
6
6
9
1
A
1
6
E
E
ED
16
E
F
1
B
1
C
1
6
6
E
1
6
6
6
Address
S
S
e
e
r
r
i
i
a
a
l
l
I
I
/
/
O
O
r
m
e
g
o
i
d
s
t
e
r
e
(
g
S
i
I
O
t
e
)
r
A-D control register 1 (AD1)
A-D control register 2 (AD2)
Timer 5 (T5)
T
m
e
r
T
m
e
r
T
m
e
r
Timer 3 (T3)
T
m
e
r
T
m
e
r
T
m
e
r
I
2
C
d
a
I
2
C
a
d
i
i
i
6
1
2
(
(
(
T
T
T
6
1
2
)
)
)
C
C
a
a
p
p
t
t
i
i
o
o
n
n
d
d
a
a
t
t
a
a
r
r
e
e
g
g
i
i
s
s
t
t
e
e
r
r
1
2
(
(
C
C
D
D
1
2
)
)
Caption position register (CPS)
Data slicer test register 2
Data slicer test register 1
S
n
c
h
r
o
n
o
u
s
s
i
g
C
D
l
a
o
c
t
a
k
c
r
l
u
o
n
c
-
k
i
n
p
d
o
e
s
t
t
e
i
o
c
t
r
r
e
e
g
g
i
i
s
s
t
t
e
e
r
r
(
(
C
D
R
P
D
S
)
)
i
n
R
e
g
i
s
t
e
r
Data slicer control register 1 (DSC1)
D
t
a
s
l
i
c
e
r
c
o
n
t
r
o
l
a
r
e
g
i
s
t
e
r
2
(
D
S
C
2
)
i
i
i
4
m
m
(
o
o
T
d
d
4
e
e
)
r
r
e
e
g
g
i
i
s
s
t
t
e
e
r
r
1
2
(
(
T
T
M
M
1
2
)
)
t
d
a
e
s
h
s
i
f
t
r
r
e
e
g
g
i
i
s
t
t
e
r
r
(
S
S
0
0
D
)
I
2
C control register (S1D)
I
2
C
c
l
o
c
k
c
o
n
CPU mode register (CPUM)
t
r
o
l
r
e
g
i
s
t
e
r
(
S
2
)
In
Interrupt request register 2 (IREQ2)
In
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
In
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
1
(
I
R
E
Q
1
)
g
g
i
i
s
s
t
t
e
e
r
r
1
2
(
(
I
I
C
C
O
O
N
N
1
2
)
)
y
n
a
l
c
o
u
n
t
e
r
r
e
g
i
s
t
e
r
(
H
C
)
b
7
b
0
Bit allocation
State immediately after reset
b7
b
0
I
S
F
R
1
A
r
e
a
(
a
d
d
r
e
s
s
e
s
E
0
1
6
t
o
F
F
1
6
)
e
r
s
(
S
M
)
I
2
C status register (S1)
r
s
s
e
(
)
: “0” immediately after reset
:
I
n
a
d
t
e
e
t
e
r
r
m
s
i
n
t
a
t
e
i
m
m
e
d
i
a
t
e
l
y
f
r
e
e
0
1
<State immediately after reset>
: “1” immediately after reset
:
:
F
(
F
(
i
x
o
t
n
h
i
s
t
b
w
i
r
t
i
t
t
o
e
“
“
0
1
”
”
)
d
o
:
<
B
i
t
a
l
l
o
c
a
t
i
o
n
>
F
u
n
c
t
i
o
n
b
i
t
: No function bit
i
x
o
t
n
h
i
s
t
b
w
i
r
t
i
t
t
o
e
“
“
1
0
”
”
)
d
o
Name
:
1
0
T
M
2
0
T
M
2
1
TM22
TM23
T
M
2
4
T
M
1
0
T
M
1
1
TM12
TM13
T
M
1
4
CM2
M
TM1R
IN
1
M
IN
1
TM2R
T
3
R
T
M
R
4
R
O
S
D
VSCR
IN3R
ICK0
R
DSR
S1R
M
T
1
E
TM2E
S
T
3
E
TM4E
O
IN
S
D
E
VSCE
E
D
E
S1E
2
E
TM25
00
16
0
0
00
16
F
1
7
1
F
1
7
1
6
6
6
6
07
16
TM15
T
M
1
6
T
M
M
1
7
TM26
T
2
7
S
D
A
D
0
SAD1
S
A
L
D
2
SAD3
S
A
B
D
4
S
R
S
A
D
5
SAD6
RBW
R
L
B
A
0
AAS
A
PIN
T
X
MST
S
E
C
M
BC0
C
0
BC1
C
0
BC2
C
ESO
C
1
ALS
C
1
B
E
L
0
B
L
1
R
0
R
1
R
2
R
3
R
4
A
K
00
16
1
00
16
00
16
3C
16
CKR
IICR
TM56R
IN
3
M
5
E
CKE
IICE
T
6
E
TM56C
C
7
C
M
5
CM6
SM0
SM1
SM2
SM3
ADC10
ADC11
ADC12
ADC14
ADC20
ADC21
ADC22
ADC25
SM5
SM6
ADC24ADC23
10BIT
SAD
F
A
S
M
O
T
E
D
0
0
1
9
1
6
0
1
6
0
1
6
F
1
6
DSC10
1
D
S
2
C
1
D
S
C
1
DSC20
D
D
S
C
2
3
DSC24
D
L
D
D
S
C
2
5
CRD3
CRD4
C
R
D
5
CRD6
C
R
D
7
DPS3
DPS4
DPS5
DPS6
DPS7
CPS0
CPS3
CPS4
CPS5
CPS1
CPS2
CPS6
CPS7
H
C
0
H
C
3
HC4
H
C
5
HC1
HC2
0
0
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
6
CDH10
CDH13
CDH14
CDH15
CDH11
CDH12
CDH16
CDH17
CDL10
C
L
1
3
C
1
4
C
L
1
5
C
D
L
1
1
CDL12
CDL16
C
D
L
1
7
00
16
00
16
0
1
6
0
1
6
0
1
6
00
16
00
16
00
16
00
16
D
1
D2
D
3
D
4
D
5
D
6
D7
D
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ACK
BIT
6
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