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參數(shù)資料
| 型號(hào)： | M37270MF-106SP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| 中文描述： | 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器 |
| 文件頁數(shù)： | 51/94頁 |
| 文件大?。?/td> | 1551K |
| 代理商： | M37270MF-106SP |
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MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
51
Notes 1 :
1T
C
(T
C
: OSD clock cycle divided by prescaler) gap oc-
curs between the horizontal display start position set by
the horizontal position register and the most left dot of the
1st block. Accordingly, when 2 blocks have different pre-
divide ratios, their horizontal display start position will not
match.
2 :
The horizontal start position is based on the OSD clock
source cycle selected for each block. Accordingly, when 2
blocks have different OSD clock source cycles, their hori-
zontal display start position will not match.
Fig. 57. Notes on horizontal display start position
(3) Dot Size
The dot size can be selected by a block unit. The dot size in vertical
direction is determined by dividing H
SYNC
in the vertical dot size con-
trol circuit. The dot size in horizontal is determined by dividing the
following clock in the horizontal dot size control circuit : the clock
gained by dividing the OSD clock source (data slicer clock, OSC1) in
the pre-divide circuit. The clock cycle divided in the pre-divide circuit
is defined as 1T
C
.
The dot size of the layer 1 is specified by bits 6 to 3 of the block
control register.
The dot size of the layer 2 is specified by the following bits : bits 3
and 4 of the block control register, bit 6 of the clock source control
register. Refer to Figure 50 (the structure of the block control regis-
ter), refer to Figure 59 (the structure of the clock source control reg-
ister).
The block diagram of dot size control circuit is shown in Figure 58.
Notes 1 :
The pre-divide ratio = 3 cannot be used in the CC mode.
2 :
The pre-divide ratio of the OSD mode block on the layer 2
must be same as that of the CC mode block on the layer 1
by bit 6 of the clock source control register.
3 :
In the bi-scan mode, the dot size in the vertical direction is
2 times as compared with the normal mode. Refer to “(13)
Scan Mode” about the scan mode.
Fig. 58. Block diagram of dot size control circuit
H
SYNC
1T
C
1T
C
Block 1 (Pre-divide ratio =1, clock source =data slicer clock)
1T
C
1T
C
4T
OSC
N
4T
OSC’
N
Note 1
Note 2
Block 2 (Pre-divide ratio =2, clock source =data slicer clock)
Block 3 (Pre-divide ratio =3, clock source =data slicer clock)
Block 4 (Pre-divide ratio =3, clock source =OSC1)
Data slicer clock
H
SYNC
OSC1
CS
0
Synchronization
Cycle
2
Cycle
3
Pre-divide circuit
Clock cycle
= 1T
C
Horizontal dot size
control circuit
Vertical dot size
control circuit
OSD control circuit
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37270MF107SP | 制造商:MITS 功能描述:* |
| M37270MF-167SP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37270MF-168SP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37270MF-XXXSP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37271EF | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
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