參數(shù)資料
型號： M37270MF-106SP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù)： 14/94頁
文件大?。?/td> 1551K
代理商： M37270MF-106SP
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
14
TIMERS
The M37270MF-XXXSP has 6 timers: timer 1, timer 2, timer 3,
timer 4, timer 5, and timer 6. All timers are 8-bit timers with the 8-bit
timer latch. The timer block diagram is shown in Figure 8.
All of the timers count down and their divide ratio is 1/(n+1), where n
is the value of timer latch. The value is set to a timer at the same time
by writing a count value to the corresponding timer latch (addresses
00F0
16
to 00F3
16
: timers 1 to 4, addresses 020C
16
and 020D
16
:
timers 5 and 6).
The count value is decremented by 1. The timer interrupt request bit
is set to “1” by a timer overflow at the next count pulse after the count
value reaches “00
16
”.
(1) Timer 1
Timer 1 can select one of the following count sources:
f(X
IN
)/16 or f(X
CIN
)/16
f(X
IN
)/4096 or f(X
CIN
)/4096
External clock from the P4
2
/TIM2 pin
The count source of timer 1 is selected by setting bits 5 and 0 of the
timer mode register 1 (address 00F4
16
). Either f(X
IN
) or f(X
CIN
) is
selected by bit 7 of the CPU mode register.
Timer 1 interrupt request occurs at timer 1 overflow.
(2) Timer 2
Timer 2 can select one of the following count sources:
f(X
IN
)/16 or f(X
CIN
)/16
Timer 1 overflow signal
External clock from the P4
2
/TIM2 pin
The count source of timer 2 is selected by setting bits 4 and 1 of the
timer mode register 1 (address 00F4
16
). Either f(X
IN
) or f(X
CIN
) is
selected by bit 7 of the CPU mode register. When timer 1 overflow
signal is a count source for the timer 2, the timer 1 functions as an 8-
bit prescaler.
Timer 2 interrupt request occurs at timer 2 overflow.
(3) Timer 3
Timer 3 can select one of the following count sources:
f(X
IN
)/16 or f(X
CIN
)/16
f(X
CIN
)
External clock from the P4
3
/TIM3 pin
The count source of timer 3 is selected by setting bit 0 of the timer
mode register 2 (address 00F5
16
) and bit 6 at address 00C7
16
. Ei-
ther f(X
IN
) or f(X
CIN
) is selected by bit 7 of the CPU mode register.
Timer 3 interrupt request occurs at timer 3 overflow.
(4) Timer 4
Timer 4 can select one of the following count sources:
f(X
IN
)/16 or f(X
CIN
)/16
f(X
IN
)/2 or f(X
CIN
)/2
f(X
CIN
)
The count source of timer 3 is selected by setting bits 4 and 1 of the
timer mode register 2 (address 00F5
16
). Either f(X
IN
) or f(X
CIN
) is
selected by bit 7 of the CPU mode register. When timer 3 overflow
signal is a count source for the timer 4, the timer 3 functions as an 8-
bit prescaler.
Timer 4 interrupt request occurs at timer 4 overflow.
(5) Timer 5
Timer 5 can select one of the following count sources:
f(X
IN
)/16 or f(X
CIN
)/16
Timer 2 overflow signal
Timer 4 overflow signal
The count source of timer 3 is selected by setting bit 6 of the timer
mode register 1 (address 00F4
16
) and bit 7 of the timer mode regis-
ter 2 (address 00F5
16
). Either f(X
IN
) or f(X
CIN
) is selected by bit 7 of
the CPU mode register.
Timer 5 interrupt request occurs at timer 5 overflow.
(6) Timer 6
Timer 6 can select one of the following count sources:
f(X
IN
)/16 or f(X
CIN
)/16
Timer 5 overflow signal
The count source of timer 6 is selected by setting bit 7 of the timer
mode register 1 (address 00F4
16
). Either f(X
IN
) or f(X
CIN
) is selected
by bit 7 of the CPU mode register. When timer 5 overflow signal is a
count source for the timer 6, the timer 5 functions as an 8-bit prescaler.
Timer 6 interrupt request occurs at timer 6 overflow.
At reset, timers 3 and 4 are connected by hardware and “FF
16
” is
automatically set in timer 3; “07
16
” in timer 4. The f(X
IN
)
8
/16 is se-
lected as the timer 3 count source. The internal reset is released by
timer 4 overflow at these state, the internal clock is connected.
At execution of the STP instruction, timers 3 and 4 are connected by
hardware and “FF
16
” is automatically set in timer 3; “07
16
” in timer 4.
However, the f(X
IN
)
8
/16 is not selected as the timer 3 count source.
So set both bit 0 of the timer mode register 2 (address 00F5
16
) and
bit 6 at address 00C7
16
to “0” before the execution of the STP in-
struction (f(X
IN
)
8
/16 is selected as the timer 3 count source). The
internal STP state is released by timer 4 overflow at these state, the
internal clock is connected.
Because of this, the program starts with the stable clock.
8
: When bit 7 of the CPU mode register (CM
7
) is “1,” f(X
IN
) be-
comes f(X
CIN
).
The structure of timer-related registers is shown in Figure 7.
相關(guān)PDF資料
PDF描述
M37270MF-167SP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
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M37271EF-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
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參數(shù)描述
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