參數(shù)資料
型號(hào): M37207MF-XXXSP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP64
封裝: 0.750 INCH, 1.78 MM PITCH, PLASTIC, DIP-64
文件頁(yè)數(shù): 50/121頁(yè)
文件大?。?/td> 1907K
代理商: M37207MF-XXXSP
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34
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
sBit 5: Bus Busy Flag (BB)
This bit indicates the status of use of the bus system. When this bit is
set to “0,” this bus system is not busy and a START condition can be
generated. When this bit is set to “1,” this bus system is busy and the
occurrence of a START condition is disabled by the START condi-
tion duplication prevention function (Note).
This flag can be written by software only in the master transmission
mode. In the other modes, this bit is set to “1” by detecting a START
condition and set to “0” by detecting a STOP condition. When the
ESO bit of the I2C control register (address 00DC16) is “0” and at
reset, the BB flag is kept in the “0” state.
s Bit 6: Communication Mode Specification Bit (transfer direction
specification bit: TRX)
This bit decides the direction of transfer for data communication. When
this bit is “0,” the reception mode is selected and the data of a trans-
mitting device is received. When the bit is “1,” the transmission mode
is selected and address data and control data are output into the
SDA in synchronization with the clock generated on the SCL.
When the ALS bit of the I2C control register (address 00DC16) is “0”
in the slave reception mode is selected, the TRX bit is set to “1”
__
(transmit) if the least significant bit (R/W bit) of the address data trans-
__
mitted by the master is “1.” When the ALS bit is “0” and the R/W bit is
“0,” the TRX bit is cleared to “0” (receive).
The TRX bit is cleared to “0” in one of the following conditions.
When arbitration lost is detected.
When a STOP condition is detected.
When occurence of a START condition is disabled by the START
condition duplication prevention function (Note).
With MST = “0” and when a START condition is detected.
With MST = “0” and when ACK non-return is detected.
At reset
s Bit 7: Communication Mode Specification Bit (master/slave speci-
fication bit: MST)
This bit is used for master/slave specification for data communica-
tion. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are received,
and data communication is performed in synchronization with the
clock generated by the master. When this bit is “1,” the master is
specified and a START condition and a STOP condition are gener-
ated, and also the clocks required for data communication are gen-
erated on the SCL.
The MST bit is cleared to “0” in one of the following conditions.
Immediately after completion of 1-byte data transmission when ar-
bitration lost is detected
When a STOP condition is detected.
When occurence of a START condition is disabled by the START
condition duplication preventing function (Note).
At reset
Note: The START condition duplication prevention function disables
the START condition generation, reset of bit counter reset,
and SCL output, when the following condition is satisfied:
a START condition is set by another master device.
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