參數(shù)資料
型號： M37207MF-XXXSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, 1.78 MM PITCH, PLASTIC, DIP-64
文件頁數(shù)： 41/121頁
文件大?。?/td> 1907K
代理商： M37207MF-XXXSP
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
26
Fig. 19. Serial I/O Timing (for LSB first)
____
Internal clock : The SRDY signal goes to HIGH during the write cycle
by writing data into the serial I/O register (address 00DD16). After the
____
write cycle, the SRDY signal goes to “L” (receive enable state). The
____
SRDY
signal goes to “H” at the next falling edge of the transfer clock
for the serial I/O register.
The serial I/O counter is set to “7” during write cycle into the serial I/
O register (address 00DD16), and transfer clock goes HIGH forcibly.
At each falling edge of the transfer clock after the write cycle, serial
data is output from the SOUT pin. Transfer direction can be selected
by bit 5 of the serial I/O mode register. At each rising edge of the
transfer clock, data is input from the SIN pin and data in the serial I/O
register is shifted 1 bit.
After the transfer clock has counted 8 times, the serial I/O counter
becomes “0” and the transfer clock stops at HIGH. At this time the
interrupt request bit is set to “1.”
External clock : When an external clock is selected as the clock source,
the interrupt request is set to “1” after the transfer clock has counted
8 counts. However, transfer operation does not stop, so the clock
should be controlled externally. Use the external clock of 1 MHz or
less with a duty cycle of 50%.
The serial I/O timing is shown in Figure 19. When using an external
clock for transfer, the external clock must be held at “H” for initializing
the serial I/O counter. When switching between an internal clock and
an external clock, do not switch during transfer. Also, be sure to ini-
tialize the serial I/O counter after switching.
Notes 1: On programming, note that the serial I/O counter is set by
writing to the serial I/O register with the bit managing in-
structions such as SEB and CLB.
2: When an external clock is used as the synchronous clock,
write transmit data to the serial I/O register when the trans-
fer clock input level is HIGH.
Synchronous clock
Transfer clock
Serial I/O register
write signal
Serial I/O output
SOUT
D0
D1
D2
D3
D4
D5
D6
D7
(See note)
Serial I/O input
SIN
Note : When an internal clock is selected, the S OUT pin is at high-impedance after transfer is completed.
Interrupt request bit is set to “1”
Receive
signal
enable
SRDY
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