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參數(shù)資料
| 型號： | M368L6423ETM |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR SDRAM Unbuffered Module |
| 中文描述： | DDR SDRAM的緩沖模塊 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大小： | 287K |
| 代理商： | M368L6423ETM |
DDR SDRAM
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
AC Timing Parameters and Specifications
Parameter
Symbol
- C5(DDR466@CL=3)
Unit
Note
Min
60
70
40
18
18
10
15
2
4.3
6
0.45
0.45
-0.55
-0.65
-
0.9
0.4
0.72
0
0.25
0.4
0.2
0.2
0.35
Max
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Internal write to read command delay
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tWTR
ns
ns
ns
ns
ns
ns
ns
tCK
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ps
tCK
tCK
tCK
tCK
70K
Clock cycle time
CL=3.0
CL=2.5
tCK
10
12
0.55
0.55
+0.55
+0.65
0.4
1.1
0.6
1.28
16
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
Write preamble setup time
Write preamble
Write postamble
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tWPST
tDSS
tDSH
tDQSH
13
5
0.6
4
tCK
DQS-in low level width
Address and Control Input setup time
Address and Control Input hold time
tDQSL
tIS
tIH
0.35
0.6
tCK
ns
h,7~10
h,7~10
0.6
ns
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
DQ & DM setup time to DQS, slew rate 0.5V/ns
DQ & DM hold time to DQS, slew rate 0.5V/ns
DQ & DM input pulse width
Control & Address input pulse width for each input
tHZ
tLZ
tMRD
tDS
tDH
tDIPW
tIPW
-
tAC max
tAC max
ns
ns
tCK
ns
ns
ns
ns
us
us
3
3
tAC min
2
0.4
0.4
1.75
2.2
i, j
i, j
9
9
Refresh interval time
Up to 128Mb
tREFI
7.8
6
256Mb, 512Mb, 1Gb
Output DQS valid window
tQH
tHP
-tQHS
min
tCH/tCL
-
ns
12
Clock half period
tHP
-
ns
11, 12
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M368L6423ETM-CCC4 | DDR SDRAM Unbuffered Module |
| M368L6423ETN-A2 | DDR SDRAM Unbuffered Module |
| M368L6423ETN-AA | DDR SDRAM Unbuffered Module |
| M368L6423ETN-B0 | DDR SDRAM Unbuffered Module |
| M368L6423ETN-CB3 | DDR SDRAM Unbuffered Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M368L6423ETM-CC5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:184pin Unbuffered Module based on 256Mb E-die 64/72-bit ECC/Non ECC |
| M368L6423ETM-CCC4 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module |
| M368L6423ETM-LC5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:184pin Unbuffered Module based on 256Mb E-die 64/72-bit ECC/Non ECC |
| M368L6423ETN-A2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module |
| M368L6423ETN-AA | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module |
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