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參數(shù)資料
| 型號(hào)： | M368L6423ETM-LC5 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 184pin Unbuffered Module based on 256Mb E-die 64/72-bit ECC/Non ECC |
| 中文描述： | 184pin緩沖模塊，基于256Mb電子模具64/72-bit ECC的/非ECC |
| 文件頁數(shù)： | 11/19頁 |
| 文件大小： | 287K |
| 代理商： | M368L6423ETM-LC5 |
DDR SDRAM
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Output Load Circuit (SSTL_2)
Output
Z0=50
C
LOAD
=30pF
V
REF
=0.5*V
DDQ
R
T
=50
V
tt
=0.5*V
DDQ
AC Operating Conditions
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
VIH(AC)
VIL(AC)
VREF + 0.31
V
V
VREF - 0.31
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
VID(AC)
VIX(AC)
0.7
VDDQ+0.6
0.5*VDDQ+0.2
V
V
1
2
0.5*VDDQ-0.2
Input/Output Capacitance
(VDD=2.6V, VDDQ=2.6V, TA= 25
°
C, f=1MHz)
Parameter
Symbol
M368L3223ETM
Min
49
42
42
25
6
6
-
M381L3223ETM
Min
51
44
44
25
6
6
6
Unit
Max
57
50
50
30
7
7
-
Max
60
53
53
30
7
7
7
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0)
Input capacitance( CS0)
Input capacitance( CLK0, CLK1,CLK2)
Input capacitance(DM0~DM7, DM8(for ECC))
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
CIN1
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
pF
pF
pF
pF
pF
pF
pF
Parameter
Symbol
M368L6423ETM
Min
65
42
42
28
10
10
-
M381L6423ETM
Min
69
44
44
28
10
10
10
Unit
Max
81
50
50
34
12
12
-
Max
87
53
53
34
12
12
12
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0,CKE1)
Input capacitance( CS0, CS1)
Input capacitance( CLK0, CLK1,CLK2)
Input capacitance(DM0~DM7, DM8(for ECC))
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
CIN1
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
pF
pF
pF
pF
pF
pF
pF
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| M368L6423ETN-A2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Unbuffered Module |
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