參數(shù)資料
型號(hào)： M368L1624DTM-CCC
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 184pin Unbuffered Module based on 256Mb D-die 64/72-bit Non ECC/ECC
中文描述： 184pin緩沖模塊的256Mb的D為基礎(chǔ)的非ECC的模具64/72-bit / ECC的
文件頁(yè)數(shù)： 19/22頁(yè)
文件大小： 354K
代理商： M368L1624DTM-CCC
DDR SDRAM
Rev. 1.2 May. 2003
128MB, 256MB, 512MB Unbuffered DIMM
Command Truth Table
(V=Valid, X=Don
′
t Care, H=Logic High, L=Logic Low)
COMMAND
CKEn-1
CKEn
CS
RAS
CAS
WE
BA0,1
A10/AP
A0 ~ A9
A11, A12
Note
Register
Register
Extended MRS
Mode Register Set
Auto Refresh
H
H
X
X
H
L
L
L
L
L
L
L
L
L
OP CODE
OP CODE
1, 2
1, 2
3
3
3
3
Refresh
H
L
L
L
H
X
Self
Refresh
Entry
Exit
L
H
L
H
L
H
X
L
H
X
H
H
X
H
X
Bank Active & Row Addr.
H
X
V
Row Address
(A0~A9, A11, A12)
L
H
L
H
X
L
H
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
H
X
L
H
L
H
V
Column
Address
4
4
4
Write &
Column Address
H
X
L
H
L
L
V
Column
Address
4, 6
7
Burst Stop
H
X
L
H
H
L
Precharge
Bank Selection
All Banks
H
X
L
L
H
L
V
X
X
5
Active Power Down
Entry
H
L
H
L
X
H
L
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
Exit
L
H
Precharge Power Down Mode
Entry
H
L
X
Exit
L
H
DM
H
X
8
9
9
No operation (NOP) : Not defined
H
X
H
L
X
H
X
H
X
Note :
1. OP Code : Operand Code. A
0
~ A
12
& BA
0
~ BA
1
: Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA
0
~ BA
1
: Bank select addresses.
If both BA
0
and BA
1
are "Low" at read, write, row active and precharge, bank A is selected.
If BA
0
is "High" and BA
1
is "Low" at read, write, row active and precharge, bank B is selected.
If BA
0
is "Low" and BA
1
is "High" at read, write, row active and precharge, bank C is selected.
If both BA
0
and BA
1
are "High" at read, write, row active and precharge, bank D is selected.
5. If A
10
/AP is "High" at row precharge, BA
0
and BA
1
are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
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