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參數(shù)資料
| 型號： | M34W02 |
| 廠商： | 意法半導體 |
| 元件分類： | DRAM |
| 英文描述： | 2Kbit Serial EEPROM with Software Data Protection(2Mb串行EEPROM) |
| 中文描述： | 2Kbit串行EEPROM與軟件數(shù)據(jù)保護（處理器串行EEPROM中） |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 152K |
| 代理商： | M34W02 |
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance (SDA)
8
pF
C
IN
Input Capacitance (other pins)
6
pF
Z
WCL
WP Input Impedance
V
IN
< 0.3 V
CC
5
20
K
Z
WCH
WP Input Impedance
V
IN
< 0.7 V
CC
500
K
t
LP
Low-pass filter input time constant
(SDA and SCL)
200
500
ns
Note:
1. Sampled only, not 100% tested.
Table 5. Input Parameters
(1)
(T
A
= 25
°
C, f = 400 kHz )
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
≤
V
IN
≤
V
CC
±
2
μ
A
I
LO
Output Leakage Current
0V
≤
V
OUT
≤
V
CC
SDA in Hi-Z
±
2
μ
A
I
CC
Supply Current
V
= 5V, f
= 400kHz
(Rise/Fall time < 10ns)
2
mA
V
CC
= 1.8V, f
C
= 400kHz
1
mA
I
CC1
Supply Current (Standby)
V
IN
= V
SS
or V
CC
,
V
CC
= 5V
100
μ
A
V
IN
= V
SS
or V
CC
,
V
CC
= 5V, f
C
= 400kHz
300
μ
A
I
CC2
Supply Current (Standby)
V
IN
= V
SS
or V
CC
,
V
CC
= 1.8V
30
μ
A
V
IN
= V
SS
or V
CC
,
V
CC
= 1.8V, f
C
= 400kHz
100
μ
A
V
IL
Input Low Voltage (SCL, SDA)
–0.5
0.3 V
CC
V
V
IH
Input High Voltage (SCL, SDA)
0.7 V
CC
6.5
V
V
IL
Input Low Voltage (E0-E2, WC)
–0.5
0.5
V
V
IH
Input High Voltage (E0-E2, WC)
V
CC
– 0.5
6.5
V
V
OL
Output Low Voltage
I
OL
= 3mA, V
CC
= 1.8V
0.4
V
Table 6. DC Characteristics
(T
A
= 0 to 70
°
C or –40 to 85
°
C; V
CC
= 4.5V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
DEVICE OPERATIONS
(cont’d)
memory on the bus will identify the device code and
compare the following 3 bits to its chip enable
inputs E2, E1, E0.
The 8th bit sent is the read or write bit (RW ), this
bit is set to ’1’ for read and ’0’ for write operations.
If a match is found, the corresponding memory will
acknowledge the identification on the SDA bus
during the 9th bit time. If the memory does not
match the device select code, it will self-deselect
from the bus and go into standby mode.
Write Operations
Following a START condition the master sends a
device select code with the RW bit set to ’0’. The
memory acknowledges it and waits for a byte ad-
dress, which provides access to the 256 bytes of
the memory area. After receipt of the byte address,
the memory again responds with an acknowledge
and waits for the data byte.
5/17
M34W02
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