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參數(shù)資料
| 型號： | M34W02 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 2Kbit Serial EEPROM with Software Data Protection(2Mb串行EEPROM) |
| 中文描述： | 2Kbit串行EEPROM與軟件數(shù)據(jù)保護（處理器串行EEPROM中） |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 152K |
| 代理商： | M34W02 |
Mode
RW bit
WC
Bytes
Initial Sequence
Current Address Read
’1’
X
1
START, Device Select, RW = ’1’
Random Address Read
’0’
X
1
START, Device Select, RW = ’0’, Address,
’1’
X
reSTART, Device Select, RW = ’1’
Sequential Read
’1’
X
1 to 256
Similar to Current or Random Mode
Byte Write
’0’
V
IL
(2)
1
START, Device Select, RW = ’0’
Page Write
’0’
V
IL
(2)
16
START, Device Select, RW = ’0’
Notes:
1. X = V
IH
or V
IL
2. WC input level is don’t care if the data to modify is in a non-write protected area. Read also the ’Write Protection using the Protect
Register paragraph.
Table 4. Operating Modes
(1)
Device Type Identifier
Chip Enable
RW
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Memory Area Device Select Code
1
0
1
0
E2
E1
E0
RW
Protect Register Device Select Code
0
1
1
0
E2
E1
E0
RW
Note:
The MSB b7 is sent first.
Table 3. Device Select Code
Power On Reset: V
CC
lock out write protect.
In order to prevent any possible data corruption and
inadvertent write operations during power up, a
Power On Reset (POR) circuit is implemented.
Until the V
CC
voltage has reached the POR thresh-
old value, the internal reset is active, all operations
are disabled and the device will not respond to any
command. In the same way, when V
CC
drops from
the operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V
CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTIONS
Serial Clock (SCL)
. The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to V
CC
to act as a pull up (see Figure 3).
Serial Data (SDA)
. The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to V
CC
to act as pull up (see Figure 3).
Chip Enable (E2 - E0)
. These chip enable inputs
are used to set the 3 least significant bits (b3, b2,
b1) of the 7 bit device select code. These inputs
may be driven dynamically or tied to V
CC
or V
SS
to
establish the device select code.
Write Control (WC
). A hardware Write Control pin
(WC), and a Protect Register, is provided on pin 7
of the M34W02. This feature is useful to protect a
part or the entire contents of the memory from any
erroneous erase/write cycle. The Write Control sig-
nal is used to enable (WC = V
IL
) or disable (WC =
V
IH
) write instructions to the protected memory
area and to the Protect Register. When uncon-
nected, the WC input is internally read as V
IH
and
neither the protected memory area nor the Protect
Register will be alterable.
3/17
M34W02
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