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參數(shù)資料
| 型號： | M34F04-WMN6TP |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 4Kbit Serial I2C Bus EEPROM With Hardware Write Control on Top Half of Memory |
| 中文描述： | 4Kbit串行I2C總線的EEPROM，帶有硬件寫控制記憶的上半部分 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 262K |
| 代理商： | M34F04-WMN6TP |
9/20
M34F04
condition until the end of the address byte), the de-
vice replies to the data bytes with NoAck, as
shown in Figure 6, and the locations are not mod-
ified. After each byte is transferred, the internal
byte address counter (the 4 least significant ad-
dress bits only) is incremented. The transfer is ter-
minated by the bus master generating a Stop
condition.
Figure 7. Write Mode Sequences with WC=0 (data write enabled)
S
S
BYTE WRITE
DEV SEL
BYTE ADDR
DATA IN
WC
S
PAGE WRITE
DEV SEL
BYTE ADDR
DATA IN 1
DATA IN 2
WC
DATA IN 3
AI02804B
PAGE WRITE
(cont'd)
WC (cont'd)
S
DATA IN N
ACK
R/W
ACK
ACK
ACK
ACK
ACK
ACK
R/W
ACK
ACK
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