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參數(shù)資料
| 型號： | M34D64WMNT6 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 64/32 Kbit Serial IC Bus EEPROM With Hardware Write Control on Top Quarter of Memory |
| 中文描述： | 64/32千位串行IC總線EEPROM，帶有硬件寫控制記憶的熱門季 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 119K |
| 代理商： | M34D64WMNT6 |
M34D64, M34D32
8/15
After the last memory address, the address
counter ‘rolls-over’ and the memory continues to
output data from the start of the memory block.
Acknowledge in Read Mode
In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9
th
bit time. If the master does not pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its standby state.
shown in Figure 8,
without
acknowledging the byte
output.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master
does
acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must
not
acknowledge the last
byte output, and
must
generate a STOP condition.
The output data comes from consecutive
addresses, with the internal address counter
automatically incremented after each byte output.
Figure 8. Read Mode Sequences
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1
st
and 4
th
bytes) must be identical.
S
DEV SEL *
BYTE ADDR
BYTE ADDR
S
DEV SEL
DATA OUT 1
AI01105C
DATA OUT N
S
S
CURRENT
ADDRESS
READ
DEV SEL
DATA OUT
RANDOM
ADDRESS
READ
S
S
DEV SEL *
DATA OUT
SEQUENTIAL
CURRENT
READ
S
DATA OUT N
S
DEV SEL *
BYTE ADDR
BYTE ADDR
SEQUENTIAL
RANDOM
READ
S
DEV SEL *
DATA OUT 1
S
ACK
R/W
NO ACK
ACK
R/W
ACK
ACK
ACK
R/W
ACK
ACK
ACK
NO ACK
R/W
NO ACK
ACK
ACK
ACK
R/W
ACK
ACK
R/W
ACK
NO ACK
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