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參數(shù)資料
| 型號： | M34D64WMNT1 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | EEPROM |
| 英文描述： | 64/32 Kbit Serial IC Bus EEPROM With Hardware Write Control on Top Quarter of Memory |
| 中文描述： | 64/32千位串行IC總線EEPROM，帶有硬件寫控制記憶的熱門季 |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 119K |
| 代理商： | M34D64WMNT1 |
3/15
M34D64, M34D32
valid V
CC
must be applied before applying any
logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a
slower clock, the master must have an open drain
output, and a pull-up resistor must be connected
from the SCL line to V
CC
. (Figure 3 indicates how
the value of the pull-up resistor can be calculated).
In most applications, though, this method of
synchronization is not employed, and so the pull-
up resistor is not necessary, provided that the
master has a push-pull (rather than open drain)
output.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to
transfer data in or out of the memory. It is an open
drain output that may be wire-OR’ed with other
open drain or open collector signals on the bus. A
pull up resistor must be connected from the SDA
bus to V
CC
. (Figure 3 indicates how the value of
the pull-up resistor can be calculated).
Chip Enable (E2, E1, E0)
These chip enable inputs are used to set the value
that is to be looked for on the three least significant
bits (b3, b2, b1) of the 7-bit device select code.
These inputs must be tied to V
CC
or V
SS
to
establish the device select code.
Write Control (WC)
The hardware Write Control pin (WC) is useful for
protecting the top quarter of the memory (as
shown in Figure 4) from inadvertent erase or write.
The Write Control signal is used to enable
(WC=V
IL
) or disable (WC=V
IH
) write instructions to
the top quarter of the memory area. When
unconnected, the WC input is internally read as
V
IL
, and write operations are allowed.
DEVICE OPERATION
The memory device supports the I
2
C protocol.
This is summarized in Figure 5, and is compared
with other serial bus protocols in Application Note
AN1001
. Any device that sends data on to the bus
is defined to be a transmitter, and any device that
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus
AI01665
VCC
CBUS
SDA
RL
MASTER
RL
SCL
CBUS
100
0
4
8
12
16
20
CBUS (pF)
M
)
10
1000
fc = 400kHz
fc = 100kHz
Figure 4. Memory Map of Write Control Areas
AI03114
80h
40h
1FFh
Write Controlled
Area
100h
000h
M34D64
FFh
Write Controlled
Area
C0h
00h
M34D32
80h
180h
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