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參數(shù)資料
| 型號： | M34C02-LBN6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2 Kbit Serial IC Bus EEPROM For DIMM Serial Presence Detect |
| 中文描述： | 2千位串行IC總線的EEPROM內(nèi)存串行存在檢測 |
| 文件頁數(shù)： | 8/19頁 |
| 文件大?。?/td> | 147K |
| 代理商： | M34C02-LBN6T |
M34C02
8/19
Setting the Protection, Using the Protection
Register
The M34C02 has a software write-protection
function, using the Protecton Register, that allows
the bottom half of the memory area (addresses
00h to 7Fh) to be permanently write protected. The
write protection feature is activated by writing once
to the Protection Register (with the WC input held
at V
SS
).
The Protection Register is accessed with the
device select code set to 0110b (as shown in
Table 3), and the E2-E1-E0 bits set according to
the states being applied to the E2-E1-E0 pins. As
The sequence, as shown in Figure 7, is:
– Initial condition: a Write is in progress.
– Step 1: the master issues a START condition
followed by a Device Select Code (the first byte
of the new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no Ack will be returned and the
master goes back to Step 1. If the memory has
terminated the internal write cycle, it responds
with an Ack, indicating that the memory is ready
to receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).
Figure 9. Read Mode Sequences
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1
st
and 3
rd
bytes) must be identical.
S
DEV SEL *
BYTE ADDR
S
DEV SEL
DATA OUT 1
AI01942
DATA OUT N
S
S
CURRENT
ADDRESS
READ
DEV SEL
DATA OUT
RANDOM
ADDRESS
READ
S
S
DEV SEL *
DATA OUT
SEQUENTIAL
CURRENT
READ
S
DATA OUT N
S
DEV SEL *
BYTE ADDR
SEQUENTIAL
RANDOM
READ
S
DEV SEL *
DATA OUT 1
S
ACK
R/W
NO ACK
ACK
R/W
ACK
ACK
R/W
ACK
ACK
ACK
NO ACK
R/W
NO ACK
ACK
ACK
R/W
ACK
ACK
R/W
ACK
NO ACK
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