參數(shù)資料
型號(hào): M34C02-WMN6T
廠商: 意法半導(dǎo)體
英文描述: 2 Kbit Serial IC Bus EEPROM For DIMM Serial Presence Detect
中文描述: 2千位串行IC總線的EEPROM內(nèi)存串行存在檢測(cè)
文件頁(yè)數(shù): 1/19頁(yè)
文件大?。?/td> 147K
代理商: M34C02-WMN6T
1/19
December 1999
M34C02
2 Kbit Serial I2C Bus EEPROM
For DIMM Serial Presence Detect
PSDIP8 (BN)
0.25 mm frame
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
8
1
8
1
8
1
I
Two Wire I
2
C Serial Interface
Supports 400 kHz Protocol
I
Single Supply Voltage:
– 2.5V to 5.5V for M34C02-W
– 2.2V to 5.5V for M34C02-L
I
Software Data Protection for lower 128 bytes
I
BYTE and PAGE WRITE (up to 16 bytes)
I
RANDOM and SEQUENTIAL READ Modes
I
Self-Timed Programming Cycle
I
Automatic Address Incrementing
I
Enhanced ESD/Latch-Up Protection
I
1 Million Erase/Write Cycles (minimum)
I
40 Year Data Retention (minimum)
DESCRIPTION
The M34C02 is a 2 Kbit serial EEPROM memory
able to lock permanently the data in its first half
(from location 00h to 7Fh). This facility has been
designed specifically for use in DRAM DIMMs
(dual interline memory modules) with Serial
Presence Detect. All the information concerning
the DRAM module configuration (such as its
access speed, its size, its organization) can be
kept write protected in the first half of the memory.
This bottom half of the memory area can be write-
protected using a specially designed software
write protection mechanism. By sending the
device a specific sequence, the first 128 bytes of
Figure 1. Logic Diagram
AI01931
3
E0-E2
SDA
VCC
M34C02
WC
SCL
VSS
Table 1. Signal Names
E0, E1, E2
Chip Enable Inputs
SDA
Serial Data/Address Input/
Output
SCL
Serial Clock
WC
Write Control
V
CC
Supply Voltage
V
SS
Ground
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