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參數(shù)資料
| 型號： | M34C00MN |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 3 x 128 bit Serial IC Bus EEPROM For ee-Tags |
| 中文描述： | 3 × 128位串行IC總線的EEPROM為電子工程，標簽 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大小： | 114K |
| 代理商： | M34C00MN |
9/15
M34C00
Table 5. DC Characteristics
(T
A
= –40 to 85 °C; V
CC
= 2.5 to 5.5 V)
Symbol
Parameter
Table 6. AC Characteristics
Note: 1. For a reStart condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
Test Condition
Min.
Max.
Unit
I
LI
Input Leakage
Current
SCL, SDA
0 V
≤
V
IN
≤
V
CC
± 2
μA
I
LO
Output Leakage Current
0 V
≤
V
OUT
≤
V
CC,
SDA in Hi-Z
± 2
μA
I
CC
Supply Current
V
CC
=5.5V, f
c
=400kHz (rise/fall time <
30ns)
2
mA
V
CC
=2.5V, f
c
=400kHz (rise/fall time <
30ns)
1
mA
I
CC1
Supply Current
(Stand-by)
V
IN
= V
SS
or
V
CC
, V
CC
= 5.5 V
2
μA
V
IN
= V
SS
or
V
CC
, V
CC
= 2.5 V
1
μA
V
IL
Input Low
Voltage
SCL, SDA
–0.3
0.3V
CC
V
V
IH
Input High
Voltage
SCL, SDA
0.7V
CC
V
CC
+1
V
V
OL
Output Low
Voltage
I
OL
= 3 mA, V
CC
= 5.5 V
0.4
V
I
OL
= 2.1 mA, V
CC
= 2.5 V
0.4
V
Symbol
Alt.
Parameter
M34C00
Unit
V
CC
=2.5 to 5.5V
T
A
= –40 to 85°C
Min
Max
t
CH1CH2
t
R
Clock Rise Time
300
ns
t
CL1CL2
t
F
Clock Fall Time
300
ns
t
DH1DH2 2
t
R
SDA Rise Time
20
300
ns
t
DL1DL2 2
t
F
SDA Fall Time
20
300
ns
t
CHCL
t
HIGH
Clock Pulse Width High
600
ns
t
CLCH
t
LOW
Clock Pulse Width Low
1.3
μs
t
CHDX 1
t
SU:STA
START Set-up Time
600
ns
t
DLCL
t
HD:STA
START Hold Time
600
ns
t
DXCX
t
SU:DAT
SDA In Set-up Time
100
ns
t
CLDX
t
HD:DAT
SDA In Hold Time
0
μs
t
CHDH
t
SU:STO
STOP Set-up Time
600
ns
t
DHDL
t
BUF
Time the bus must be free between STOP and next START
1.3
μs
t
CLQV 3
t
AA
Clock Low to SDA Out Valid
200
900
ns
t
CLQX
t
DH
SDA Out Hold Time after Clock Low
200
ns
f
C
f
SCL
Clock Frequency
400
kHz
t
W
t
WR
Write Time
10
ms
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