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參數(shù)資料
| 型號(hào)： | M34C00MN |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 3 x 128 bit Serial IC Bus EEPROM For ee-Tags |
| 中文描述： | 3 × 128位串行IC總線的EEPROM為電子工程，標(biāo)簽 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大小： | 114K |
| 代理商： | M34C00MN |
M34C00
2/15
Figure 2A. SO and TSSOP Connections
Note: 1. NC = Not Connected
1
2
3
4
AI03395B
8
7
6
5
SDA
VSS
SCL
NC
NC
NC
NC
VCC
M34C00
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Power On Reset: V
CC
Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V
CC
has reached the POR
threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when V
CC
drops from the operating
voltage, below the POR threshold value, all
operations are disabled and the device will not
respond to any command. A stable and valid V
CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
This signal is used to strobe all data in and out of
the device. In applications where this line is used
by slave devices to synchronize the bus to a
slower clock, the bus master must have an open
drain output, and a pull-up resistor must be
connected from Serial Clock (SCL) to V
CC
. (Figure
3 indicates how the value of the pull-up resistor
can be calculated). In most applications, though,
this method of synchronization is not employed,
and so the pull-up resistor is not necessary,
provided that the bus master has a push-pull
(rather than open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
These devices are compatible with the I
2
C
memory standard. This is a two wire serial
interface that uses a bi-directional data bus and
serial clock. The device carries a built-in 4-bit
Device Type Identifier code (1010) in accordance
with the I
2
C bus definition to access the memory
area and a second Device Type Identifier code
(0110) to access the Protection Register.
The device behaves as a slave in the I
2
C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are
initiated by a Start condition, generated by the bus
master. The Start condition is followed by a Device
Select code and RW bit (as described in Table 3),
terminated by an acknowledge bit.
When writing data to the memory, the device
inserts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
Table 2. Absolute Maximum Ratings
1
Note: 1.
Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. IPC/JEDEC J-STD-020A
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500
, R2=500
)
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
–40 to 85
°C
T
STG
Storage Temperature
–65 to 150
°C
T
LEAD
Lead Temperature during Soldering
SOT23: t.b.d.
SO: 20 seconds (max)
2
TSSOP: 20 seconds (max)
2
t.b.d.
235
235
°C
V
IO
Input or Output range
–0.6 to 6.5
V
V
CC
Supply Voltage
–0.3 to 6.5
V
V
ESD
Electrostatic Discharge Voltage (Human Body model)
3
4000
V
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