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參數(shù)資料
| 型號(hào)： | M3488 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 256 x 256 DIGITAL SWITCHING MATRIX |
| 中文描述： | 256 × 256數(shù)字切換矩陣 |
| 文件頁(yè)數(shù)： | 9/18頁(yè) |
| 文件大?。?/td> | 193K |
| 代理商： | M3488 |
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GENERAL DESCRIPTION
TheM3488isintendedforlargetelephoneswitching
systems,mainly centralexchanges,digitalline con-
centrators and private branch exchanges where a
distributed microcomputer control approach is ex-
tensively used. It consists of a speech memory
(SM), a controlmemory (CM), a serial/paralleland
a parallel/serial converter, an internal parallel bus,
an interface (8 data lines, 11 control signals) and
dedicatedcontrollogic.
Bymeans of repeatedclock divisiontwo timebases
are generated. These are preset from an external
synchronization signal to two specific count num-
bers so that sequentialscanning of the basesgive
synchronous addresses to the memories and I/O
channel controls. Different preset count numbers
are needed because of processing delays and
datapathdirection.Thetimebasefortheinputchan-
nels is delayed and the timebase for output chan-
nels is advancedwith respect to theactualtime.
Eachserial PCM input channelis converted to par-
allel data and stored in the speech memory at the
beginning of any new time slot (according to first
timebase) in the location determined by input pin
numberandtime slot number.The control memory
CM maintainsthe correspondencesbetween input
and output channels.More exactly, for any output
pin/outputchannelcombinationthecontrolmemory
gives either the fulladdress of the speechmemory
location involved in the PCM transfer or an 8-bit
word to besuppliedto theparallel/serialoutputcon-
verter. A9
th
bitateachCM locationdefinesthedata
sourcefor outputlinks, low for SM, high for CM.
The late timebase is used to scan the outputchan-
nelsand to determinethe pins to beservicedwithin
eachchannel; enoughidle cycles are leftto the mi-
croprocessorfor asynchronousinstructionprocess-
ing.
Two8-bit registers OR1and OR2supply feedback
dataforcontrolordiagnosticpurposes;OR1comes
from internal busi.e. frommemories, OR2 gives an
opcode copyand additionaldata to the microcom-
puter. A four byte-five bit stack register and an in-
struction register, under microcomputer control,
store input data available at theinterface.
Dedicatedlogic,undercontrolofthemicroprocessor
interface, extractsthe 0 channelcontentof any se-
lected PCM input bus, using spare cycles of SM.
M3488
9/18
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M3488B1 | 256 x 256 DIGITAL SWITCHING MATRIX |
| M3493B2 | CMOS 12 X 8 CROSSPOINTWITH CONTROL MEMORY |
| M3493B1 | CMOS 12 X 8 CROSSPOINTWITH CONTROL MEMORY |
| M34A08-VDW6T | 2 Kbit Serial SMBus EEPROM for ACR Card Configuration |
| M34C00 | SWITCH TACT 6MM SQ L=5.85MM160GF |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M3488B1 | 制造商:STMicroelectronics 功能描述: |
| M3488Q1 | 制造商:STMicroelectronics 功能描述: |
| M3489PS-H300-B300 | 制造商:Bonitron 功能描述:REGULATOR FOR VFDS |
| M34-8L | 制造商:BOWIN 制造商全稱:BOWIN 功能描述:SINGLE OUTPUT LED FLASHER IC |
| M348X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UM348x Multi-Instrument Melody Generator |
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