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參數(shù)資料
| 型號(hào)： | M3488 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 256 x 256 DIGITAL SWITCHING MATRIX |
| 中文描述： | 256 × 256數(shù)字切換矩陣 |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 193K |
| 代理商： | M3488 |
Internaltimebasesareforcedby synchronismtoan
assignedcountnumberinordertorestore channels
and bit sequential addressing to a known state.
Count difference between the bases is 32, corre-
spondingtotwotimeslots,thatistheminimum PCM
propagationtime,or latencytime.
INP PCM 7 to INPPCM 0
PCM input bussesor pins ; they accept a standard
2Mbit/s rate. Bit 1 (sign bit) is the first of the serial
sequence; ina parallel conversionit isleft adjusted
as the most significantdigit.
OUT PCM 7 to OUT PCM 0
PCM output busses or pins ; bit rate and organiza-
tionare the same as inputpins.
Outputbuffersare open drain CMOS .
The device drives the outputchannelstheoretically
one bit time before theycan be exploited as logical
input channels (bit and slot compatibility is pre-
served):this featureallows inputsand outputstobe
tied togethercancelling any analogdelay of digital
outputsup to
t
DEL max
= t
bit
- t
PD(PCM)max
+ t
PD(PCM)min
MIXEDRD and WR OPERATIONS
In principle RD and WR operations are allowed in
any orderwithin specificationconstraints.
In practive,only one controlpin is low at any given
time when CS1 and CS2 are enabled.
If by mistake or hardware failure both RD and WR
pins are low, the interfacebus is internally pushed
to tristatecondition as long as WR is held low and
input registers are protected.
Registers OR1 and OR2 can be read in any order
with a single RD strobe using C/D as multiplexing
control; nevertheless thisprocedure isnot recom-
mendedbecausethe deviceis directedfor instruc-
tionflow only accordingto datalatchedbyRD rising
edge.
MultipleRDoperationsof thesamekindareallowed
without affecting the instruction flow : only ”new”
OR1 or OR2read operationsstep theflow.
Input and output registers are held for sure in the
previous state for the first 3 cyclesfollowing an op-
code or an OR2 read.
FUNCTIONAL DESCRIPTION OF SPECIFIC MICROPROCESSOR OPERATIONS
Thedevice,undermicroprocessorcontrol,performs
the followinginstructions :
1CHANNEL CONNECTION
2CHANNEL DISCONNECTION
3LOADINGOF A BYTE ON A PCM OUTPUT
CHANNEL
4 TRANSFER OF A SINGLEPCM OUTPUT
CHANNEL SAMPLE
5 TRANSFER OF A SINGLEOUTPUT
CHANNEL CONTROL WORD
6TRANSFEROFASELECTED0CHANNEL PCM
INPUT DATA ACCORDING TO AN 8-BIT MASK
PREVIOUSLY STORED IN THE ”EXPECTED
MESSAGES” REGISTER
The instruction flowis asfollows.
Any input protocol is startedby themicroprocessor
interface loading the internal stack register with 2
bytes(4 bytes for instructions 1 and 3) qualified as
databytes by C/D = 0 and a specific opcodequali-
fied by C/D = 1 (match condition is normally
needed).
After thecode is loadedin the instruction registerit
is immediately checked to see whether it is ac-
ceptableand if not it is rejected. If accepted the
instructionis alsoprocessedas regardsmatch con-
dition and is appended for execution during the
memories’ spare cycles.
Fourcases arepossible :
a)thecodeis notvalid;executioncannottakeplace,
the DR outputpin is reset to indicate the error ; all
registersare saved ;
b) thecodeis valid for types 2, 4 and6 butit is un-
matched;executioncannottakeplace,DR isnotaf-
fected.
c) the code is valid for types 1 and 3 and it is un-
matched; theinstructionis interpretedas achannel
disconnection.
d) the code is valid and is either matchedor of type
5 ; the instruction is processedas received.
Validationcontroltakesonlytwocyclesoutofa total
executiontime of 4to 7cycles ; the lastoperationis
updatingof the contentof registers OR1and OR2,
accordingto the following instructiontables.
M3488
12/18
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