53
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Skip condition
Detailed description
C
52
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Function
Mnemonic
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Hexadecimal
notation
Type of
instructions
Parameter
N
w
N
c
Instruction code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Transfers the contents of the high-order 2 bits of timer 1 to register W5, and transfers the contents of
the low-order 8 bits of timer 1 to registers A and B.
When stopping (W1
0
=0), transfers the contents of register W5 to the contents of the high-order 2 bits of
timer 1 and of the timer 1 reload register, and transfers the contents of registers A and B to the contents
of the low-order 8 bits of timer 1 and of the timer 1 reload register.
When operating (W1
0
=1), transfers the contents of register W5 to the contents of the high-order 2 bits
of the timer 1 reload register, and transfers the contents of registers A and B to the contents of the low-
order 8 bits of the timer 1 reload register.
Transfers the contents of timer 2 to registers A and B.
Transfers the contents of registers A and B to timer 2 and timer 2 reload register.
Transfers the contents of registers A and B to timer 2 reload register.
Transfers the contents of timer 3 to registers A and B.
Transfers the contents of registers A and B to timer 3 and timer 3 reload register R3L.
Transfers the contents of registers A and B to timer 3 reload register R3H.
TAB1
T1AB
TAB2
T2AB
TR2AB
TAB3
T3AB
T3HAB
T
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
0
0
1
0
0
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
1
0
1
0
1
0
0
1
1
1
0
0
1
0
1
0
0
0
1
1
0
0
1
0
1
0
0
0
1
1
1
1
0
1
2 7 0
2 3 0
2 7 1
2 3 1
2 3 A
2 7 2
2 3 2
2 3 D
(W5)
←
(T1
9
, T1
8
)
(B)
←
(T1
7
–T1
4
)
(A)
←
(T1
3
–T1
0
)
At timer 1 stop (W1
0
=0),
(R1
9
, R1
8
)
←
(W5)
(T1
9
, T1
8
)
←
(W5)
(R1
7
–R1
4
)
←
(B)
(T1
7
–T1
4
)
←
(B)
(R1
3
–R1
0
)
←
(A)
(T1
3
–T1
0
)
←
(A)
At timer 1 operating (W1
0
=1),
(R1
9
, R1
8
)
←
(W5)
(R1
7
–R1
4
)
←
(B)
(R1
3
–R1
0
)
←
(A)
(B)
←
(T2
7
–T2
4
)
(A)
←
(T2
3
–T2
0
)
(R2
7
–R2
4
)
←
(B)
(T2
7
–T2
4
)
←
(B)
(R2
3
–R2
0
)
←
(A)
(T2
3
–T2
0
)
←
(A)
(R2
7
–R2
4
)
←
(B)
(R2
3
–R2
0
)
←
(A)
(B)
←
(T3
7
–T3
4
)
(A)
←
(T3
3
–T3
0
)
(R3L
7
–R3L
4
)
←
(B)
(T3
7
–T3
4
)
←
(B)
(R3L
3
–R3L
0
)
←
(A)
(T3
3
–T3
0
)
←
(A)
(R3H
7
–R3H
4
)
←
(B)
(R3H
3
–R3H
0
)
←
(A)
MACHINE INSTRUCTIONS (CONTINUED)