![](http://datasheet.mmic.net.cn/120000/M34570EDFP_datasheet_3558674/M34570EDFP_68.png)
System Clock
67
Under
development
Preliminary Specifications REV.1.02
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
Figure 1.8.2. CM0 register
Symbol
Address
When reset
CM0
000616
0000 X0002
System clock control register 01
CM00
CM01
CM02
Clock output function
select bit2
In WAIT peripheral
function clock stop bit
Port XC switch bit
Main clock (XIN-XOUT)
stop bit5
CM04
CM05
CM06
CM07
Nothing is assigned. When write, should set to "0".
When read, its content is indeterminate.
RW
Function
Bit name
Bit
symbol
RW
0 : Main clock oscillation
1 : Main clock stop6
0 0 : I/O port P53
0 1 : fC output
1 0 : f8 output
1 1 : f32 output
0 : I/O port function
1 : XCIN-XCOUT oscilation function4
Watchdog timer
function select bit
System clock select bit8
0 : Select XIN - XOUT
1 : Select XCIN - XCOUT
0 : Watchdog timer interrupt
1 : Reset7
Notes :
1. The PRC0 bit in the PRCR register should be set to "1" (write enable) before rewriting to the CM0
register.
2. When the PM07 bit in the PM0 register is set to "0" (BCLK output), the CM01 to CM00 bits should be
set to "002". When the PM15 to PM14 bits in the PM1 register is set to "012" (ALE output to P53), the
CM01 to CM00 bits should be set to "002". When the PM07 bit is set to "1" (function selected in the
CM01 to CM00 bits) in microprocessor or memory expansion mode, the CM01 to CM00 bits should
be set to "002" to output "L" from port P53 (port P53 does not function as an I/O port).
3. fc32 is not stopped. When setting the CM02 bit to "1", the PLL clock cannot be used in wait mode.
4. When setting the CM04 bit to "1" (XCIN-XCOUT oscillation), the PD8_7 to PD8_6 bits should be set to
"002" (with port P87 and P86 input mode) and the PU25 bit in the PUR2 register be set to "0" (no pull-
up).
5. To enter low-power consumption mode or ring oscillator low power consumption mode, the CM05 bit
stops the main clock. The CM05 bit cannot detect whether the main clock stops or not. To stop the
main clock, the CM05 bit should be set to "1" after the CM07 bit is set to "1" with a stable sub clock
oscillation or after the CM21 bit in the CM2 register is set to "1" (ring oscillator clock). When setting
the CM05 bit to "1" (main clock stop), XOUT is set to "H". Also, an internal feedback resistance
remains ON. XIN is pulled up to XOUT ("H" level) via feedback resistance.
6. When setting the CM05 bit to "1", the MCD4 to MCD0 bits in the MCD register are set to "010002"
(divide-by-8 mode). In ring oscillation mode, the MCD register is not divided by eight even if XIN-Xout
is terminated by the CM05 bit.
7. Once the CM06 bit is set to "1", it cannot be set "0" by program.
8. After setting the CM04 bit to "1" with a stable sub clock oscillation, the CM07 bit should be changed
"0" to "1".
After setting the CM05 bit to "0" with a stable main clock oscillation, the CM07 bit should be changed
"1" to "0".
Avoid setting the CM07 bit and CM04 or CM05 bits simultaneously.
b7
b6
b5
b4
b3
b2
b1
b0
b1 b0
0 : Peripheral clock does not stop in
wait mode
1 : Peripheral clock stops in wait
mode3