參數(shù)資料
型號(hào)： M34570M4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO36
封裝： 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-36
文件頁數(shù)： 49/69頁
文件大?。?/td> 687K
代理商： M34570M4-XXXFP
Under
development
Preliminary Specifications REV.1.02
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
54
Bus
Table 1.7.2. Each Processor Mode and Port Function
(Separate bus)
(All space multiplex bus)
Single-chip
mode
Memory expansion mode/microprocessor mode
Memory
expansion mode
Data bus width
of space
to be accessed
"012", "102""002"
"112" 1
Some 16-bit
external space
All 8-bit
external space
Notes :
1. Avoid setting the PM05 to PM04 bits to "112" (all CS space as multiplex bus) in microprocessor mode because running a
separate bus after reset.
When selecting "112" in memory expansion mode, address bus accesses with 64K bytes per chip-select.
2. Address bus is selected in seprarete bus configuration.
3. The ALE output pin should be selected by the PM15 to PM14 bits in the PM1 register. Either "WRL,WRH" or "BHE,WR"
should be selected by the PM02 bit in the PM0 register.
4. When selecting the DRAMC and accessing the DRAM space, CASL, CASH, DW and BCLK output occurs.
5. The CS signal and address bus should be determined by the PM11 to PM10 bits in the PM1 register.
Processor
mode
PM05 to
PM04 bits in
PM0 register
CS (chip-select) or address bus (A23)
(Refer to the paragraph "Bus control" for details) 5
RD, WRL, WRH and BCLK output or RD, BHE, WR and BCLK output
(Refer to the paragraph "Bus control" for details) 3,4
CS (chip-select) or address bus (A23)
(Refet to the paragraph "Bus control" for details) 5
P00 to P07
P10 to P17
Data bus
D0 to D7
I/O port
P20 to P27
I/O port
Address bus
data bus 2
A0/D0 to A7/D7
I/O port
P30 to P37
I/O port
Address bus/
data bus 2
A8/D8 to A15/D15
P40 to P43
I/O port
P44 to P46
I/O port
P47
I/O port
P50 to P53
I/O port
P54
I/O port
P55
I/O port
P56
I/O port
P57
I/O port
HDLA 3
HOLD
RAS 3
RDY
CS1 or CS2 as multiplex bus.
Another as separate bus
HDLA 3
RAS 3
(
)
Data bus
D0 to D7
Data bus
D0 to D7
Data bus
D0 to D7
Address bus
data bus 2
A0/D0 to A7/D7
Address bus
A0/D0 to A7/D7
Address bus
A0/D0 to A7/D7
Address bus
data bus
A0/D0 to A7/D7
Address bus
data bus
A0/D0 to A7/D7
Address bus
A8 to A15
Address bus
A8 to A15
Address bus
A8 to A15
Address bus
A8 to A15
Address bus
A16 to A19
Address bus
A16 to A19
Address bus
A16 to A19
Address bus
A16 to A19
Data bus
D8 to D15
Data bus
D8 to D15
Address bus/
data bus
A8/D8 to A15/D15
Some 16-bit
external space
All 8-bit
external space
Some 16-bit
external space
All 8-bit
external space
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