參數(shù)資料
型號(hào): M34570EDFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, MICROCONTROLLER, PDSO36
封裝: 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-36
文件頁數(shù): 25/32頁
文件大?。?/td> 319K
代理商: M34570EDFP
M65762FP
REJ03F0235-0200 Rev.2.00 Sep 14, 2007
Page 31 of 34
Table B.1
Host Bus I/F Timing Characteristics
(Unit: ns)
Timing Conditions
Abbreviation
Item
Min
Typ
Max
t0
RESET* assert time
100
t1
CS* setup time to RD* assert
15
t2
CS* hold time to RD* negate
15
t3
A0 to 3 setup time to RD* assert
15
t4
RD* assert time
20
t5
A0 to 3 hold time to RD* negate
15
t6
D0 to 7 output determination time to RD* assert
0
20
t7
D0 to 7 output hold time to RD* negate
0
20
t11
CS* setup time to WR* assert
15
t12
CS* hold time to WR* negate
15
t13
A0 to 3 setup time to WR* assert
15
t14
WR* assert time
15
t15
A0 to 3 hold time to WR* negate
15
t16
D0 to 7 input setup time to WR* negate
20
t17
D0 to 7 input hold time to WR* negate
5
Table B.2
Timing Characteristics of Code Data Bus I/F
Timing Conditions
Abbreviation
Item
Min
Typ
Max
t20
CDRQ negate time to CDAK* assert
15
t21
CDAK* setup time to CDRD* assert
15
t22
CDAK* hold time to CDRD* negate
15
t24
CDRD* assert time
20
t26
CD0 to 31 output determination time to CDRD* assert
0
20
t27
CD0 to 31 output hold time to CDRD* negate
0
20
t31
CDAK* setup time to CDWR* assert
15
t32
CDAK* hold time to CDWR* negate
15
t34
CDWR* assert time
15
t36
CD0 to 31 input setup time to CDWR* negate
15
t37
CD0 to 31 input hold time to CDWR* negate
5
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