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參數(shù)資料
| 型號： | M34570EDFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, MICROCONTROLLER, PDSO36 |
| 封裝： | 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-36 |
| 文件頁數(shù)： | 22/32頁 |
| 文件大?。?/td> | 319K |
| 代理商： | M34570EDFP |
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29
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Program counter (PC) ............................................................................................
Address 0 in page 0 is set to program counter.
Interrupt enable flag (INTE) ...................................................................................
Power down flag (P) ...............................................................................................
External 0 interrupt request flag (EXF0) ................................................................
Interrupt control register V1 ...................................................................................
Interrupt control register V2 ...................................................................................
Interrupt control register I1 ....................................................................................
Timer 1 interrupt request flag (T1F) ......................................................................
Timer 2 interrupt request flag (T2F) ......................................................................
Timer 3 interrupt request flag (T3F) ......................................................................
Watchdog timer flags (WDF1, WDF2) ...................................................................
Watchdog timer enable flag (WEF) .......................................................................
Timer control register W1 ......................................................................................
Timer control register W2 ......................................................................................
Timer control register W3 ......................................................................................
Timer count value store register W5 .....................................................................
Clock control register MR ......................................................................................
8-bit general-purpose register SI ...........................................................................
Carrier wave output control register C2 .................................................................
Key-on wakeup control register K0 .......................................................................
Pull-up control register PU0 ...................................................................................
Carry flag (CY) .......................................................................................................
Register A ..............................................................................................................
Register B ..............................................................................................................
Register D ..............................................................................................................
Register E ..............................................................................................................
Register X ..............................................................................................................
Register Y ..............................................................................................................
Register Z ...............................................................................................................
Stack pointer (SP) ..................................................................................................
(2) Internal state at reset
Table 12 shows port state at reset, and Figure 26 shows
internal state at reset (they are retained after system is
released from reset).
Name
D0–D8, D9/TOUT
P00–P03
P10–P13
P20, P21/INT
P30–P33
P40–P43
CARR
State
High impedance (Note 1)
“H” (VDD) level (Note 1)
High impedance
High impedance (Note 1)
High impedance (Note 2)
“L” (VSS) level
Function
D0–D8, D9
P00–P03
P10–P13
P20, P21
P30–P33
P40–P43
CARR
Table 12 Port state at reset
The contents of timers, registers, flags and RAM except those
shown in Figure 26 are undefined, so set the initial values to
them.
Notes 1: Output latch is set to “1.”
2: The pull-up transistor is turned off.
Fig. 26 Internal state at reset
0
000
0
!!! !!! !!
00
0
“!” represents undefined.
0
(Interrupt disabled)
0
(Interrupt disabled)
0
(Interrupt disabled)
000
0
(Prescaler and timer 1 stopped)
0
(Timer 2 stopped)
0
(Timer 3 stopped)
00
10
0
00
0
00
000
0
00
0
00
0
000
0
!! !
00
0
000
0
!!
11
1
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